NGD2VER
NGD2VER translates your design into a Verilog HDL file containing a netlist description of your design in terms of Xilinx simulation primitives. You can use the Verilog file to perform a back-end simulation with a Verilog simulator.
Simulation is based on SIMPRIMs, which create simulation models using basic simulation primitives. For example, a primitive for the XC4000 dual-port RAM does not exist in the Verilog SIMPRIM library files. Instead, if a dual-port RAM is needed, NGD2VER builds a simulation model for the dual-port RAM out of two 16x1 RAM SIMPRIM primitives.
NGD2VER can produce a Verilog file representing a design at any of the following stages.
- An unmapped design - To translate an unmapped design, the input to NGD2VER is an NGD file - a logical description of your design. The output from NGD2VER is a Verilog file containing a functional description of the design without timing information.
- A mapped, unrouted design - To translate a mapped design which has not been placed and routed, the input to NGD2VER is an NGA file - an annotated logical description of your design - generated from a mapped physical design. The output from NGD2VER is a Verilog file containing a functional description of the design, and an additional SDF (Standard Delay Format) file containing timing information. The SDF file contains component delays without routing delays.
- A routed design - To translate a design that has been placed and routed, the input to NGD2VER is an NGA file generated from a routed physical design. The output from NGD2VER is a Verilog file containing a functional description of the design and an SDF file containing both component and routing delays.
The design flow for NGD2VER is shown in the following figure.
