NGD2VER Notes

Following are some notes about NGD2VER.

• The end of the test fixture (TV) file produced by NGD2VER contains the following commands.
  
  #1000 $stop
  // #1000 $finish
  
  The $stop command terminates simulation from the test fixture and places the simulator in “interactive mode”. This mode allows you to view the waveforms produced or allows interaction with other programs that need the simulator open.
  
  You can terminate the Verilog simulator as follows.
  
  
  • In interactive mode, enter finish.
    
    
  • To exit automatically instead of entering interactive mode, edit the test fixture file to remove or comment out the $stop line and uncomment the $finish line.
    
    
• When you compile your unit-under-test design from NGD2VER along with your test fixture, there may be mismatches on bused ports.
  
  This problem occurs when your unit under test has top-level ports that are defined as LSB-to-MSB, as shown in the following example.
  
  input [0:7] A;
  
  As a result of the way your input design was converted to a netlist before it was read into the Xilinx implementation software, the Xilinx design database does not include information on how bus direction was defined in the original design. When NGD2VER writes out a structural timing Verilog description, all buses are written as MSB-to-LSB, as shown in the following example.
  
  input [7:0] A;
  
  If your ports are defined as LSB-to-MSB in your original input design and test fixture, there is a port mismatch when the test fixture is compiled for timing simulation. Use one of the following methods to solve this problem.
  
  
  • In the test fixture, modify the instantiation of the unit under test so that all ports are defined as MSB-to-LSB for timing simulation
    
    
  • Define all ports as MSB-to-LSB in your original design and test fixture. For example, enter [7:0] instead of [0:7].