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NGD2VHDL

The NGD2VHDL program translates your design into a VITAL 95 IEEE compliant VHDL file containing a netlist description of the design in terms of Xilinx simulation primitives. You can use the VHDL file to perform a back-end simulation by a VHDL simulator.

Simulation is based on SIMPRIMs, which create simulation models using basic simulation primitives. For example, a primitive for the XC4000 dual-port RAM does not exist in the VITAL SIMPRIM library files. Instead, if a dual-port RAM is needed, NGD2VHDL builds a simulation model for the dual port ram out of two 16x1 RAM SIMPRIM primitives.

NGD2VHDL produces a VHDL file representing a design in any of the following stages.

The design flow for NGD2VHDL is shown in the following figure.

Figure 18.1 NGD2VHDL Design Flow

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