Design Flow Overview

The FPGA design flow is a 3-step process that consists of the following stages.

Design Entry - In this stage of the design flow, you create your design using a Xilinx-supported schematic editor or hardware description language (HDL).
Design Implementation - By mapping to a specific Xilinx architecture, and placing and routing your design, you convert the logical design file format that you created in the design entry stage into a physical file format. The physical information is contained in the NCD (Physical Description) file. Then you create a bitstream file from the NCD file and optionally program a PROM or EPROM for subsequent programming of your Xilinx device.
Design Verification - Using a gate level simulator, the Xilinx XChecker cable^™, or the Parallel Cable III, you ensure that your design meets your timing requirements and functions properly. See the Hardware User Guide for more information about Xilinx download cables and demonstration boards.

The Xilinx design flow is shown in the following figure.

Figure 1.12 Xilinx Design Flow Overview

Overviews of the each step of the design flow process are included in the “Design Entry” chapter, the “Design Implementation” chapter, and the “Design Verification” chapter, respectively.

The full design flow is an iterative process of entering, implementing, and verifying your design until it is correct and complete. The Xilinx Development System allows quick design iterations through the design flow cycle. Since FPGA devices permit unlimited reprogramming, you do not need to discard devices when debugging your design in-circuit. See the “Design Implementation” chapter for more information.

The following table defines the terms used in the “Xilinx Design Flow Overview” figure.

Table 1_2 Design Flow Terms

Term	Description
Schematic entry	Design entry using graphic symbols
Text-based entry	Design entry using a design Hardware Description Language (HDL)
Optimization	Converting device-independent or behavioral logic descriptions to a form that can be efficiently implemented in a Xilinx FPGA
Mapping	Representing a design's logic as resources of the Xilinx FPGA
Placement	Assigning design blocks created during mapping to specific locations in the FPGA
Routing	Assigning the interconnect paths
Bitstream generation	Converting a design into a bitstream that can be loaded into a Xilinx FPGA
Back-annotation	Association of implementation net delay information with the original nets found in the input design.
Simulation	Software emulation of a design`s logic and timing using input stimuli

The following figure shows the Xilinx M1 software flow chart for FPGA design.