MAP

Mapping is the process of allocating CLBs, IOBs, or other Xilinx FPGA resources to logical elements in a design. This process is represented in “The MAP Program” figure. Because the available resources differ among different Xilinx FPGA families, the MAP program chooses different options, depending upon which device is used.

There are two types of files input to the MAP program, as follows.

• NGD file - Native Generic Database file. This file contains a logical description of the design and constraint information applied to the design during design entry or entered in a UCF (User Constraints File).
  
  
• NMC files - Macro Physical Library files. Pre-placed physical macros are integrated into a design using a .nmc representation of the macro. The .nmc macro library file is created using the EPIC physical design editor.
  
  

The PCF, or Physical Constraints File, is output by MAP. This file can be manually edited according your design needs.

Figure 3.2 The MAP Program