After your design has been routed, you need to generate the binary data which can be used to program your physical device. This is done with BitGen, Xilinx' bitstream generation program. BitGen takes a fully routed NCD (Native Circuit Description) file as its input and produces a configuration bitstream - a binary file with a .bit extension. This file contains all of the configuration information from the NCD file, defining the internal logic and interconnections of the FPGA, plus device-specific information from other files associated with the target device. The binary data in the BIT file can then be downloaded into the FPGA's memory cells or it can be used to create a PROM file. See the “BitGen” figure for a diagram of this process.
Before generating the final bitstream for production, you should run it without the -d option to create a Design Rule Checker (DRC) report. Then you should run it using -t (Tie operation) to define valid logic levels for any remaining unused interconnect in the Xilinx FPGA. For more information on BitGen, BitGen options, and configuration modes, consult the “BitGen” chapter in the Development System Reference Guide.
Within the Design Manger, BitGen is run during the configuration stage. (This process is performed with the Flow Engine interface.) BitGen options are set in the Configuration Options dialog box.
Figure 3.7 BitGen |  |
