Static Timing Analysis With TRACE

Static timing analysis is best for quick timing checks of a design after placement and routing is complete.

TRACE (Timing Reporter and Circuit Evaluator) is a Xilinx application program designed to provide static timing analysis and can be used to evaluate how well the place and route tools have met any input timing constraints. (See the “TRACE” figure for a graphical representation.)

By using TRACE, you can quickly check for timing problems in your design. You can also use TRACE to determine path delays in your design.

TRACE performs two major functions.

• Timing verification - the process of verifying that the design meets your timing constraints.
  
  
• Reporting - the process of enumerating input constraint violations and placing them into an accessible file. TRACE can be run on partially or completely placed and routed designs. The timing information reported issued by TRACE depends on the completeness of the placement and routing of the input design.
  
  

Within the Design Manager, TRACE is run using the Timing Analyzer. See the Timing Analyzer Reference/User Guide for details.