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X74_163

4-Bit Binary Counter with Parallel and Trickle Enables, Active-Low Load Enable, and Synchronous Reset

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
Macro
Macro
Macro
Macro
Macro
Macro
Macro
N/A

figures/x4178n.gif

X74_163 is a 4-stage, 4-bit, synchronous, loadable, resettable, cascadable binary counter. The active-Low synchronous reset (R), when Low, overrides all other inputs and resets the data outputs (QD, QC, QB, QA) and the ripple carry-out output (RCO) Low during the Low-to-High clock (CK) transition. When the active-Low load enable (LOAD) is Low and R is High, parallel clock enable (ENP) and trickle clock enable (ENT) are overridden and the data on inputs (A, B, C, D) is loaded into the counter during the Low-to-High clock (CK) transition. The outputs (QD, QC, QB, QA) increment when LOAD, ENP, ENT, and R are High during the Low-to-High clock transition. The counter ignores clock transitions when LOAD is High and ENP or ENT are Low; RCO is High when QD - QA and ENT are High.

The carry-lookahead design accommodates large counters without extra gating. Refer to “Carry-Lookahead Design” in the “X74_160” section for more information.

Inputs
Outputs
R
LOAD
ENP
ENT
D - A
CK
QD - QA
RCO
0
X
X
X
X

0
0
1
0
X
X
D - A

d - a
RCO
1
1
0
X
X
X
No Chg
RCO
1
1
X
0
X
X
No Chg
0
1
1
1
1
X

Inc
RCO
RCO = (QD•QC•QB•QA•ENT)
d - a = state of referenced input one setup time prior to active clock transition

Figure 11.23 X74_163 Implementation XC3000, XC4000, XC5200, Spartans

Figure 11.24 X74_163 Implementation XC9000

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