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X74_273

8-Bit Data Register with Active-Low Asynchronous Clear

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
Macro
Macro
Macro
Macro
Macro
Macro
Macro
N/A

figures/x4183n.gif

X74_273 is an 8-bit data register with active-low asynchronous clear. The active-Low asynchronous clear (CLR), when Low, overrides all other inputs and resets the data outputs (Q8 - Q1) Low. When CLR is High, the data on the data inputs (D8 - D1) is transferred to the corresponding data outputs (Q8 - Q1) during the Low-to-High clock transition (CK).

Inputs
Outputs
CLR
D8 - D1
CK
Q8 - Q1
0
X
X
0
1
D8 - D1

d8 - d1
dn = state of referenced input one setup time prior to active clock transition

Figure 11.33 X74_273 Implementation XC3000, XC4000, XC5200, XC9000, Spartans

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