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X74_390

4-Bit BCD/Bi-Quinary Ripple Counter with Negative-Edge Clocks and Asynchronous Clear

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
Macro
Macro
Macro
Macro
Macro
Macro
Macro
N/A

figures/x4189n.gif

X74_390 is a cascadable, resettable binary-coded decimal (BCD) or bi-quinary counter that can be used to implement cycle lengths equal to whole and/or cumulative multiples of 2 and/or 5. In BCD mode, the output QA is connected to negative-edge clock input (CKB), and data outputs (QD - QA) increment during the High-to-Low clock transition as shown in the truth table, provided asynchronous clear (CLR) is Low. In bi-quinary mode, output QD is connected to the negative-edge clock input (CKA). As shown in the truth table, in bi-quinary mode, QA supplies a divide-by-five output and QB supplies a divide-by-two output, provided asynchronous CLR is Low. When asynchronous CLR is High, the other inputs are overridden, and data outputs (QD - QA) are reset Low.

Larger ripple counters are created by connecting the QD output (BCD mode) or QA output (bi-quinary mode) of the first stage to the appropriate clock input of the next stage and connecting the CLR inputs in parallel.

Count
BCD
Bi-Quinary
QD
QC
QB
QA
QD
QC
QB
QA
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
2
0
0
1
0
0
1
0
0
3
0
0
1
1
0
1
1
0
4
0
1
0
0
1
0
0
0
5
0
1
0
1
0
0
0
1
6
0
1
1
0
0
0
1
1
7
0
1
1
1
0
1
0
1
8
1
0
0
0
0
1
1
1
9
1
0
0
1
1
0
0
1

Figure 11.42 X74_390 Implementation XC3000, XC4000, XC5200, Spartans

Figure 11.43 X74_390 Implementation XC9000

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