Previous

Physical Constraints


NOTE

The information in this section applies only to FPGA families.


When a design is mapped, the logical constraints found in the netlist and the UCF file are translated into physical constraints; that is, constraints that apply to a specific architecture. These constraints are found in a mapper-generated file called the Physical Constraints File (PCF). The file contains two sections, the schematic section and the user section. The schematic section contains the physical constraints based on the logical constraints found in the netlist and the UCF file. The user section can be used to add any physical constraints.

PCF File Syntax

The structure of the PCF file is as follows.

schematic start;

translated schematic and UCF or NCF constraints in PCF format

schematic end;

user-entered physical constraints

You should put all user-entered physical constraints after the “schematic end” statement.


NOTE

Do not edit the schematic constraints. They are overwritten every time the mapper generates a new PCF file.


Global constraints need not be attached to any object but should be entered in a constraints file.

The end of each constraint statement must be indicated with a semi-colon.


NOTE

In all of the constraints files (NCF, UCF, and PCF), instance or variable names that match internal reserved words will be rejected unless the names are enclosed in double quotes. It is good practice to enclose all names in double quotes. For example, the following entry would not be accepted because the word net is a reserved word.


NET net FAST;

Following is the recommended way to enter the constraint.

NET “net” FAST;

or

NET “$SIG_0” FAST ;

Syntax Descriptions

A description of each legal physical constraint follows.


NOTE

Although this section describes the constraint's syntax for the PCF file, it is preferable to place any user-generated constraint in the UCF file - not in an NCF or PCF file.


COMPGRP

Description

Identifies a group of components.

Syntax

COMPGRPgroup_name”=comp_item1... comp_itemn [EXCEPT comp_group];

where

comp_item is one of the following,

FREQUENCY

Description

Identifies the minimum operating frequency for all input pads and sequential output to sequential input pins clocked by the specified net. If no net name is given, the constraint applies to all clock nets in the design that do not have a specific clock frequency constraint.

Syntax

TSidentifier=FREQUENCY frequency_item frequency_value ;

frequency_item FREQUENCY=frequency_value;

where

frequency_item is one of the following,

frequency_value is one of the following,

INREG

Description

Forces the placement of a flip-flop or latch close to the IOB so that the two elements can be connected using fast routes. Because XC5200 IOBs do not have flip-flops or latches, you can apply this attribute to meet fast setup timing requirements if a flip-flop or latch is driven by an IOB.

Syntax

NET net_name INREG ;

where net_name is the name of the net that connects the IOB to the INREG instance.

LOCATE

Description

Specifies a single location, multiple single locations, or a location range.

Syntax

Single or multiple single locations

COMP comp_name LOCATE=[SOFT] site_item1... site_itemn [LEVEL n];

COMPGRP group_name LOCATE=[SOFT] site_item1... site_itemn [LEVEL n];

MACRO name LOCATE=[SOFT] site_item1... site_itemn [LEVEL n];

Range of locations

COMP comp_name LOCATE=[SOFT] SITEsite_name” : SITE site_name [LEVEL n];

COMPGRP group_name LOCATE=[SOFT] SITE site_name : SITE site_name [LEVEL n];

MACRO macro_name LOCATE=[SOFT] SITE site_name : SITE site_name [LEVEL n];

where

site_name is a component site (that is, a CLB or IOB location).

site_item is one of the following,

n is 0, 1, 2, 3, or 4.

LOCK

Description

Locks a net that has been previously placed or routed (that is, cannot be unplaced, unrouted, moved, swapped, or deleted). Can also be used to lock all nets.

Syntax

A specific net

“net_name” LOCK;

All nets

ROUTING LOCK;

MAXDELAY

Description

Identifies a maximum total delay for a net or path in the design. If a net is specified, the maximum delay constraint applies to all driver-to-load connections on the net. If a path is specified, the delay value is the constraint for the path including net and component delays.

Syntax

TSidentifier=MAXDELAY path path_value [PRIORITY integer];

path MAXDELAY=path_value [PRIORITY integer];

net_delay_item MAXDELAY=delay_time [units] [PRIORITY integer];

where

path is one of the following,

path_value is one of the following:

net_delay_item is one of the following:

MAXSKEW

Description

Specifies a maximum signal skew between a driver and loads on a specified clock signal. Skew is the difference between minimum and maximum load delays on a clock net. If no signal is specified, this constraint applies to all signals which have clock pins as loads and do not have a specified skew constraint.

Syntax

skew_item MAXSKEW=time [units];

where

skew_item is one of the following,

units defaults to nanoseconds, but the timing number can be followed by ps, ns, us, or ms (picoseconds, nanoseconds, microseconds, or milliseconds) to indicate the intended units.

OFFSET

Description

Specifies the timing relationship between an external clock and its associated data-in- or data-out-pin.

Can be used on a group of one or more data components or pads.

The OFFSET constraint can be a "global" constraint that applies to all data pad nets in the design for the specified clock. When the NET "name" specifier is used, the constraint is associated with a single net. When the TIMEGRP "group" specifier is used, the constraint is associated with a group of data pad nets.

Optionally, except for CPLDs, a time group qualifier, TIMEGRP "reggroup," can be added to any OFFSET constraint to indicate that the offset applies only to registers specified in the qualifying group. When used with the "Group method," the "register time" group indicates to which design registers clocked by the clock IOB the offset applies.

Syntax

Global method

OFFSET={IN | OUT} offset_time [units] {BEFORE | AFTER} NET ["clk_net"] [TIMEGRP "reggroup"];

Single net method

NET "name" OFFSET={IN | OUT} offset_time [units] {BEFORE | AFTER} NET ["clk_net"] [TIMEGRP "reggroup"];

Group method

TIMEGRP "group" OFFSET={IN | OUT} offset_time [units] {BEFORE | AFTER} NET ["clk_net"] [TIMEGRP "reggroup"];

where

group is the name of a time group containing IOB components or PAD bels.

offset_time is the external offset.

units defaults to nanoseconds, but the timing number can be followed by ps, ns, us, or ms (picoseconds, nanoseconds, microseconds, or milliseconds) to indicate the intended units.

clk_iob_name is the block name of the clock IOB.

reggroup is a previously defined time group of register BELs. Only registers in the time group clocked by the specified IOB component is checked against the specified offset time.

OUTREG

Description

Forces the placement of a flip-flop or latch close to the IOB so that the two elements can be connected using fast routes. Because XC5200 IOBs do not have flip-flops or latches, you can apply this attribute to meet fast setup timing requirements if a flip-flop or latch is driving an IOB.

Syntax

NETnet_name” OUTREG;

where net_name is the name of the net that connects the IOB to the OUTREG instance.

PATH

Description

Assigns a path specification to a path.

Syntax

PATH “path_name”=path_spec;

where

path_spec is one of the following,

group_item is one of the following,

BEL instance_name is the instance name of a basic element. Basic elements are the building blocks that make up a CLB - function generators, flip-flops, carry logic, and RAMs.

PENALIZE TILDE

Description

Penalizes those delays that are reported as only approximate (signified with a tilde (~) in delay reports) by a user-specified percentage. When the penalize tilde constraint is applied to an approximate delay, the delay will be penalized by the designated percentage in subsequent timing checks. Default for percent value is zero.

Syntax

PENALIZE TILDE=percent

PERIOD

Description

Assigns a timing period to a timing specification.

Syntax

TSidentifer=PERIOD period_item period_value [{LOW | HIGH}{time [units]| percent}];

period_item PERIOD=period_value [{LOW | HIGH}{time [units]| percent}];

where

period_item is one of the following,

period_value is one of the following,

HIGH or LOW can be optionally specified to indicate whether the first pulse is to be High or Low.

high_or_low_time is the optional High or Low time, depending on the preceding keyword. If an actual time is specified, it must be less than the period. If no High or Low time is specified, the default duty cycle is 50 percent.

hi_lo_units is an optional field to indicate the units for the duty cycle. The default is nanoseconds (ns), but the High or Low time number can be followed by ps, us, ms, or % if the High or Low time is an actual time measurement.

PIN

Description

Identifies a specific pin.

Syntax

PINpin_name”=pin_spec;

where

pin_spec is one of the following,

BEL instance_name is the instance name of a basic element. Basic elements are the building blocks that make up a CLB - function generators, flip-flops, carry logic, and RAMs.

PRIORITIZE

Description

Assigns a weighted importance to a net or bus. Values range from 0 through 100, with 100 being the highest priority and 0 the lowest. The default is 3. Any net with a priority of 3 is not considered critical; no constraint will be generated. The prioritize constraint is used by PAR, which assigns longlines by net priority and routes higher-priority nets before routing lower-priority nets. The prioritize constraint is also used by BITGEN to determine which nets not to use for tiedown. A net with a priority greater than 3 will only be used for tiedown as a last resort.

Syntax

NET "net_name" PRIORITIZE=integer;

PROHIBIT

Description

Disallows the use of a site or multiple sites within PAR, EPIC, and the CPLD fitter.

Syntax

Single or multiple single locations

PROHIBIT= site_group;

PROHIBIT= site_group1... ,site_groupn;

Range of locations

PROHIBIT= site_group : site_group;

where

site_group is one of the following,

site_name must be a valid site for the targeted device. (For example, CLB_R1C1.FFX is not a valid site for the XC4000X or SpartanXL.)


NOTE

CPLDs do not support the "Range of locations" form of PROHIBIT.


SITEGRP

Description

Identifies a group of sites.

Syntax

SITEGRP site_group_name=site_group1... site_groupn ; [EXCEPT site_group];

where

site_group is one of the following,

site_name must be a valid site for the targeted device. (For example, CLB_R1C1.FFX is not a valid site for the XC4000X or SpartanXL.)

TEMPERATURE

Description

Allows the specification of the operating temperature.


NOTE

Each architecture has its own specific range of valid operating temperatures. If the entered temperature does not fall within the supported range, the constraint is ignored and an architecture-specific default value is used instead.


Syntax

TEMPERATURE=value[C |F| K]

where

value is an integer or a real number specifying the temperature.

C, K, and F are the temperature units. F is degrees Fahrenheit, K is degrees Kelvin, and C is degrees Celsius, the default.

TIMEGRP (Timing Group)

Description

Defines objects that are to be treated as a group for timing considerations.You can refer to a group of flip-flops, input latches, pads, or RAMs by using the corresponding keywords.

Keyword
Description
FFS
CLB or IOB flip-flops only; not flip-flops built from function generators
LATCHES
CLB or IOB latches only; not latches built from function generators
PADS
Input/output pads
RAMS
For architectures with RAMS

Syntax

TIMEGRP "group_name"=[qualifier1] group_spec1... [qualifiern] group_specn [EXCEPT group_spec1... group_specn];

where

qualifier is RISING or FALLING.

group_spec is one of the following,

BEL instance_name is the instance name of a basic element. Basic elements are the building blocks that make up a CLB - function generators, flip-flops, carry logic, and RAMs.

This example shows you one way to use the TIMEGRP attribute. If you have some outputs that can be slower than others, you can create timespecs similar to those shown below for output signals obc_data(7:0) and ingr_irq_n.

First create the Timegroups.

TIMEGRP slow_outs=PADS(obc_data* : ingr_irq_n) ;

TIMEGRP fast_outs=PADS : EXCEPT : slow_outs ;

Then apply a timing spec to the Timegroups.

TIMESPEC TS08=FROM : FFS : TO : fast_outs : 22 ;

TIMESPEC TS09=FROM : FFS : TO : slow_outs : 75 ;

TIG (Timing Ignore)

Description

Identifies paths that can be ignored for timing purposes.

Syntax

ignore_item TIG [=TSidentifier1... TSidentifiern];

where

ignore_item is one of the following,

BEL instance_name is the instance name of a basic element. Basic elements are the building blocks that make up a CLB - function generators, flip-flops, carry logic, and RAMs.

For a detailed description of TIG, see the “Entering Timing Specifications” section in the Development System Reference Guide.

TSidentifier

Description

Assigns a timing period or frequency to a timing specification.

Syntax

Period

TSidentifer=PERIOD period_item period_value [{LOW | HIGH}{time [units]| percent}];

period_item PERIOD=period_value [{LOW | HIGH}{time [units]| percent}];

where

period_item is one of the following,

period_value is one of the following,

HIGH or LOW can be optionally specified to indicate whether the first pulse is to be High or Low.

high_or_low_time is the optional High or Low time, depending on the preceding keyword. If an actual time is specified, it must be less than the period. If no High or Low time is specified, the default duty cycle is 50 percent.

hi_lo_units is an optional field to indicate the units for the duty cycle. The default is nanoseconds (ns), but the High or Low time number can be followed by ps, us, ms, or % if the High or Low time is an actual time measurement.

Frequency

TSidentifier=FREQUENCY frequency_item frequency_value ;

frequency_item FREQUENCY=frequency_value;

where

frequency_item is one of the following,

frequency_value is one of the following,

VOLTAGE

Description

Allows the specification of the operating voltage. This provides a means of prorating delay characteristics based on the specified voltage.


NOTE

Each architecture has its own specific range of supported voltages. If the entered voltage does not fall within the supported range, the constraint is ignored and an architecture-specific default value is used instead.


Syntax

VOLTAGE=value[V]

where

value is an integer or real number specifying the voltage.

V specifies volts, the default voltage unit.

Next