FDS_1

D Flip-Flop with Negative-Edge Clock and Synchronous Set

FDS_1 is a single D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). The synchronous set input, when High, sets the Q output High on the High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low during the High-to-Low clock (C) transition.

The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex simulates power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_VIRTEX symbol.

Inputs			Outputs
S	D	C	Q
1	X		1
0	1		1
0	0		0