FJKCE
J-K Flip-Flop with Clock Enable and Asynchronous Clear
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Virtex
|
|---|
Macro
| Macro
| Macro
| Macro
| Macro
| Macro
| Macro
| Macro
|
FJKCE is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous clear (CLR), when High, overrides all other inputs and resets the Q output Low. When CLR is Low and CE is High, Q responds to the state of the J and K inputs, as shown in the following truth table, during the Low-to-High clock transition. When CE is Low, the clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
Inputs
| Outputs
|
|---|
CLR
| CE
| J
| K
| C
| Q
|
|---|
1
| X
| X
| X
| X
| 0
|
0
| 0
| X
| X
| X
| No Chg
|
0
| 1
| 0
| 0
| X
| No Chg
|
0
| 1
| 0
| 1
| 
| 0
|
0
| 1
| 1
| 0
|
| 1
|
0
| 1
| 1
| 1
|
| Toggle
|
