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FJKPE

J-K Flip-Flop with Clock Enable and Asynchronous Preset

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
N/A
Macro
Macro
Macro
Macro
Macro
Macro
Macro

figures/x3757n.gif

FJKPE is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous preset (PRE), when High, overrides all other inputs and sets the Q output High. When PRE is Low and CE is High, the Q output responds to the state of the J and K inputs, as shown in the truth table, during the Low-to-High clock (C) transition. When CE is Low, clock transitions are ignored.

For FPGAs, the flip-flop is asynchronously preset, output High, when global reset (GR for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The GR/GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX symbol.

For CPLDs, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

Inputs
Outputs
PRE
CE
J
K
C
Q
1
X
X
X
X
1
0
0
X
X
X
No Chg
0
1
0
0
X
No Chg
0
1
0
1

0
0
1
1
0

1
0
1
1
1

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Figure 5.42 FJKPE Implementation XC4000, XC5200, Spartans, Virtex

Figure 5.43 FJKPE Implementation XC9000

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