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ILD_1

Transparent Input Data Latch with Inverted Gate

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
Macro
Macro
Macro
Macro
N/A
Macro
Macro
Macro

figures/x4387n.gif

ILD_1 is a transparent data latch, which can be used to hold transient data entering a chip. When the gate input (G) is Low, data on the data input (D) appears on the data output (Q). Data on D during the Low-to-High G transition is stored in the latch.

The latch is asynchronously cleared with Low output when power is applied. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

For information on legal IFD, IFD_1, ILD, and ILD_1 combinations, refer to the “ILD, 4, 8, 16” section.

Inputs
Outputs
G
D
Q
0
1
1
0
0
0
1
X
d
d = state of referenced input one setup time prior to Low-to-High gate transition

Figure 6.27 ILD_1 Implementation XC3000

Figure 6.28 ILD_1 Implementation XC4000, Spartans

Figure 6.29 ILD_1 Implementation XC5200, Virtex

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