| XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Virtex |
|---|---|---|---|---|---|---|---|
| Primitive | N/A | N/A | N/A | N/A | N/A | N/A | N/A |
The OSC element's clock signal frequency is derived from an external crystal-controlled oscillator. The OSC output can be connected to an ACLK buffer, which is connected to an internal clock net.
Two dedicated input pins (XTAL 1 and XTAL 2) on each FPGA device are internally connected to pads and input/output blocks that are connected to the OSC amplifier. The external components are connected as shown in the following example. Refer to The Programmable Logic Data Book for details on component selection and tolerances.
