The following design example is used to demonstrate the basic CPLD design flow. This design implements a counter with variable start and stop values which are loaded into registers from a data input bus. When the START input is asserted, the start value is loaded into the counter and the counter outputs are enabled. The counter outputs increment on each clock cycle until the counter value matches the stop value. The counter outputs are disabled on the next clock cycle. The design can be implemented in a Xilinx XC95108-7PC84 device.
To help you understand the design, an equivalent schematic is shown in the “Schematic Representation - SCAN Design” figure.
Figure 1.2 Schematic Representation - SCAN Design |  |
Both a VHDL and a Verilog HDL version of this design are provided with the software as an example.
The VHDL source file (scan.vhd) for the scan example design is shown below.
-------------------------------------------------------------------
-- Xilinx CPLD Synopsys VHDL Tutorial Design
-- File: scan.vhd
-- Target Device: XC9536-5PC44
-- Author: Xilinx Corporation
-- Copyright (C) Xilinx Corporation 1994
-- All rights reserved
-- Requirements: Xilinx XACT Version M1
-- (Alliance core and Synopsys interface)
-- Synopsys: Design Compiler or FPGA Compiler
-- v3.4b or later
-------------------------------------------------------------------
-- Standard library configuration --
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity scan is
port (CLOCK, CLEAR, START, WRITE_START, WRITE_END : in std_logic;
DATA_IN : in std_logic_vector (7 downto 0);
C_OUT : out std_logic_vector (7 downto 0);
DONE : out std_logic);
end scan;
architecture behavioral of scan is
signal START_REG : std_logic_vector (7 downto 0);
signal END_REG : std_logic_vector (7 downto 0) := "11111111";
signal COUNT : std_logic_vector (7 downto 0) := "00000000";
signal OE_REG, DONE_REG : std_logic := '0';
-- Initial states used by behavioral simulation only.
begin
-- Starting value register.
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if (WRITE_START = '0') then
START_REG <= DATA_IN;
end if;
end if;
end process;
-- Ending value register with asynchronous preload.
process (CLEAR, CLOCK)
begin
if (CLEAR = '1') then
END_REG <= "11111111";
elsif (CLOCK'event and CLOCK='1') then
if (WRITE_END = '0') then
END_REG <= DATA_IN;
end if;
end if;
end process;
-- DONE flag and OE-control registers with asynchronous clear.
process (CLEAR, CLOCK)
begin
if (CLEAR = '1') then
DONE_REG <= '0';
OE_REG <= '0';
elsif (CLOCK'event and CLOCK='1') then
-- Registered equality comparator:
if (COUNT = END_REG) then
DONE_REG <= '1';
else
DONE_REG <= '0';
end if;
-- OE-control register:
if (START = '1') then
OE_REG <= '1';
elsif (DONE_REG = '1') then
OE_REG <= '0';
end if;
end if;
end process;
-- Counter with asynchronous clear and parallel load.
process (CLEAR, CLOCK)
begin
if (CLEAR = '1') then
COUNT <= "00000000";
elsif (CLOCK'event and CLOCK='1') then
if (START = '1') then
COUNT <= START_REG;
elsif (OE_REG = '1') then
COUNT <= COUNT + 1;
end if;
end if;
end process;
-- Three-state counter outputs.
C_OUT <= COUNT when (OE_REG = '1')
else "ZZZZZZZZ";
DONE <= DONE_REG;
end behavioral;
Typically you will enter your design in Synopsys VHDL/HDL form by using a text editor. However, all required source, setup, and test bench files for this design example have already been entered for you. The VHDL design files are contained in the $XILINX/synopsys/tutorial/cpld/vhdl directory, and the Verilog HDL design files are in $XILINX/synopsys/tutorial/cpld/verilog.
Create a local copy of the scan tutorial directory as follows:
If you need more information on design entry see the Synopsys Design Compiler manuals.
Functional simulation verifies the logic of your design. This will save you time by catching logic errors early in the development cycle. This section describes the simulation flow for the VHDL System Simulator (VSS). If you are not using VSS, skip this section and continue with step 9.
You must analyze your source design file and test bench before simulation.
Analyze the scan design by entering the following Synopsys command on the UNIX command line:
vhdlan scan.vhd
You will see the analyzer version number and a copyright notice. If the analysis works properly you will be returned to the UNIX prompt with no error messages displayed.
For this example a test bench is provided (scan_tb.vhd). At the end of this file, a configuration named CFG_SCAN_TB is declared.
Analyze the test bench for scan by entering the following Synopsys command on the UNIX command line:
vhdlan scan_tb.vhd
Again, you will see the analyzer version number and a copyright notice. If the analysis works properly you will be returned to the UNIX prompt with no error messages displayed.
The test bench for the scan design example (scan_tb.vhd) is shown below:
-------------------------------------------------------------------
-- Xilinx CPLD Synopsys VHDL Tutorial Design Test Bench
-- File: scan_tb.vhd
-- Target Device: XC9536-5PC44
-- Author: Xilinx Corporation
-- Copyright (C) Xilinx Corporation 1994
-- All rights reserved
-- Requirements: Xilinx XACT Version M1
-- (Alliance core and Synopsys interface)
-- Synopsys: VSS simulator v3.4b-vital or later
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use STD.Textio.all;
entity scan_tb is
end scan_tb;
architecture test of scan_tb is
constant tCW : time := 25 ns;
component scan
port (CLOCK, CLEAR, START, WRITE_START, WRITE_END: in std_logic;
DATA_IN: in std_logic_vector (7 downto 0);
C_OUT: out std_logic_vector (7 downto 0);
DONE: out std_logic);
end component;
signal CLOCK, CLEAR, START, WRITE_START, WRITE_END: std_logic;
signal DATA_IN: std_logic_vector (7 downto 0);
signal C_OUT: std_logic_vector (7 downto 0);
signal DONE: std_logic;
begin
UUT: scan
port map (CLOCK, CLEAR, START, WRITE_START, WRITE_END,
DATA_IN, C_OUT, DONE);
DRIVER: process
begin
CLOCK <= '0';
CLEAR <= '1';
START <= '0';
WRITE_START <= '1';
WRITE_END <= '1';
DATA_IN <= "00000000";
wait for 200 ns;
CLEAR <= '0';
wait for tCW;
CLOCK <= '1';
wait for tCW;
CLOCK <= '0';
DATA_IN <= "01111101";
WRITE_START <= '0';
wait for tCW;
CLOCK <= '1';
wait for tCW;
CLOCK <= '0';
DATA_IN <= "10000001";
WRITE_START <= '1';
WRITE_END <= '0';
wait for tCW;
CLOCK <= '1';
wait for tCW;
CLOCK <= '0';
DATA_IN <= "00000000";
WRITE_END <= '1';
START <= '1';
wait for tCW;
CLOCK <= '1';
wait for tCW;
for I in 1 to 6 loop
CLOCK <= '0';
START <= '0';
wait for tCW;
CLOCK <= '1';
wait for tCW;
end loop;
CLOCK <= '0';
START <= '1';
wait for tCW;
CLOCK <= '1';
wait for tCW;
CLOCK <= '0';
START <= '0';
wait for tCW;
CLOCK <= '1';
wait for tCW;
CLOCK <= '0';
CLEAR <= '1';
wait for tCW;
CLOCK <= '1';
wait for tCW;
CLOCK <= '0';
CLEAR <= '0';
wait for tCW;
wait;
end process;
end test;
configuration CFG_SCAN_TB of scan_tb is
for test
end for;
end CFG_SCAN_TB;
Invoke the simulator by entering the following Synopsys command on the UNIX command line:
vhdldbx &
You will see the following window for selecting the analyzed configurations:
Figure 1.3 VHDLDBX Window | |
Select CFG_SCAN_TB from the menu. This brings up the Synopsys VHDL Debugger window.
Click in the lower section of the Synopsys VHDL Debugger window and enter the following command:
trace *'signal
This command selects all signals at the test bench level for display and brings up the Dynamic Waveform Viewer (Waves).
Click the RUN button in the Debugger window to run the simulation waveform specified in the test bench. A trace display appears.
Return to the UNIX environment by selecting EXECUTE-QUIT from the VHDL Debugger menu.
If you need more information on functional simulation see the "Simulating Your Design" chapter.
Synthesizing your design converts the VHDL or Verilog HDL source text into a netlist that is composed of logic primitives. The netlist is in a form that can be read by the Xilinx fitter.
This design example demonstrates the compilation flow using dc_shell commands. You could instead use the Synopsys Design Analyzer GUI, but this is not shown in this book.
Enter the Synopsys DC Shell environment by entering the following Synopsys command on the UNIX command line:
dc_shell
You will see the DC Shell license information and command-line prompt. Verify that the software version is v3.1 or newer.
The commands required to compile the scan design example are shown in the following steps 10 through 16. These commands are also contained in compiler script files. The appropriate commands for either the Design Compiler orthe FPGA Compiler are contained in scan.script which you can run by entering the following Synopsys command:
include scan.script
If you choose to use these compiler scripts, go to step 17 when compilation is complete.
Unless otherwise specified, the commands in steps 10-16 are the same for both FPGA Compiler and Design Compiler. Unless otherwise specified, these commands are the same for either the VHDL or Verilog HDL version of the scan design.
Read and analyze your VHDL source design file by entering the following Synopsys command:
analyze -format vhdl scan.vhd
For Verilog HDL source design, enter the following command:
analyze -format verilog scan.v
The warning messages you may see during this step are normal. The VHDL source file contains initial signal values that are used only for functional simulation and these values are ignored during synthesis. Actual register initial states are set using attributes as shown in step 13.
To build the design based on your analyzed VHDL file, entering the following Synopsys command:
elaborate scan
This command displays each register and 3-state buffer encountered in your design.
To synthesize an implementation of your design based on cells in the XC9000 technology library enter the following Synopsys command:
compile -map_effort low
The mapping effort is set to LOW to save compilation time because the synthesizer does not perform any speed or area optimization for CPLD designs; optimization is performed by the CPLD fitter.
In this design we want the counter, the OE_REG and DONE flip-flop to be initialized to zero. We also want the END_REG register to initialize to all ones to prevent the comparator from detecting a false DONE condition. The initial states of the remaining flip-flops are not critical for this design.
By default, all registers in an XC9500 or XC9500XL devices are initialized to zero when powered up, so we need not specify any dc_shell directives for the counter, OE_REG or DONE. To specify the all-ones initial state of the END_REG register, enter the following Synopsys command:
set_attribute END_REG* init S -type string
The init attribute may be attached to either the flip-flop cells or their output nets in the design.
We want to constrain clock period for this design to be no more than 12 ns. Enter the following Synopsys timing constraint:
create_clock CLOCK -period 12
We want the CLOCK input for this design to be assigned to one of the global clock input pins (GCLK) of the device. Normally, the CPLD fitter would do this automatically whenever possible. To explicitly assign a global clock, enter the following Synopsys shell command:
set_pad_type -exact BUFG CLOCK
To place I/O buffer cells on all top-level ports in the design, enter the following Synopsys commands:
set_port_is_pad "*"
insert_pads
Any hierarchy in the design must be flattened before attributes can be written into the netlist. Enter the following Synopsys shell command to flatten the design:
ungroup -all -flatten
The design database is now complete and ready to be output in netlist form.
Write an EDIF-formatted netlist by entering the following Synopsys command:
write -format edif -output scan.sedif
The timing constraint entered in step 14 is written into a separate DC_shell script file which is later read by the Xilinx implementation software. Enter the following Synopsys shell command to write the timing constraint file:
write_script > scan.dc
Exit DC Shell by entering the following Synopsys command:
exit
You are returned to the UNIX prompt.
The DC_shell script file containing your timing constraints written in Step 19 must be translated into a Xilinx constraint file, scan.ncf. At the Unix prompt, enter the following command to run the translator:
dc2ncf scan.dc
If you need more information on compiling your design, see the "Compiling Your Design" chapter.
The synthesizer creates a gate-level design with no physical device information; the physical layout of the device is done in the fitter step. No speed or area estimates are provided by the XC9000 synthesis library. Therefore do not attempt to create a timing report or perform estimated timing simulation at this time.
The CPLD fitter translates your logical design file (scan.sedif) into a physical device layout, and performs all device-specific logic optimization.
This design example demonstrates the fitter flow using cpld command-line entry. You could instead use the Xilinx Design Manager GUI to process your design. This is explained in chapters 2 and 3 of this guide.
To fit your design into an XC9000 device, enter the following on the UNIX command line:
cpld scan
To fit the design into an XC9500XL device, enter the following command:
cpld -p 9500xl scan
The fitter displays a series of progress messages and a resource summary that shows how well your design fits into the target device.
When the fitter is finished, and assuming there are no errors, you need only to examine the fitter report file, scan.rpt. If you wish, you can also examine the static timing report file, scan.tim.
If you need more information on fitting, see the "Fitting Your Design" chapter.
Timing simulation uses the actual device delays based on the physical layout of your design after fitting.
The cpld command produces a timing simulation database file (scan.nga) each time the design is successfully implemented. To translate the .nga file for simulation using VSS or other VITAL simulator, enter the following command at the UNIX prompt:
ngd2vhdl -w scan scan_time
The ngd2vhdl command produces a VITAL-compliant structural VHDL file (scan_time.vhd) and an SDF-formatted timing back-annotation file (scan_time.sdf).
To translate the .nga file for simulation using a Verilog simulator, enter the following command:
ngd2ver -w scan scan_time
The ngd2ver command produces a structural Verilog file (scan_time.v) and an SDF-formatted timing book annotation file (scan_time.sdf).
The remainder of this tutorial describes the procedure for performing timing simulation using the VSS simulator. If you are not using the VSS simulator, skip the remainder of this tutorial.
Analyze the implemented design produced by the Xilinx ngd2vhdl command by entering the following Synopsys command on the UNIX command line:
vhdlan scan_time.vhd
You will see the analyzer version number and a copyright notice. If the analysis works properly you will be returned to the UNIX prompt with no error messages displayed.
Analyze the simulation test bench by entering the following Synopsys command on the UNIX command line:
vhdlan scan_tb.vhd
Again, you will see the analyzer version number and a copyright notice. If the analysis works properly you will be returned to the UNIX prompt with no error messages displayed.
Invoke the Synopsys VSS simulator by entering the following Synopsys command on the UNIX command line:
vhdldbx -sdf_top \
/SCAN_TB/UUT -sdf scan_time.sdf CFG_SCAN_TB &
This will open the simulator window. The -sdf parameter specifies the timing back-annotation file produced by ngd2vhdl. The -sdf_top parameter specifies the level in the test bench hierarchy at which the back annotation information will be applied, which is the "UUT" instance of the scan test bench.
Use the TRACE command to specify the same signals used during functional simulation in step 6. Enter the following command on the VHDL Debugger command line:
trace *'signal
This opens the Dynamic Waveform Viewer window.
Run the simulation by clicking the RUN button in the lower section of the Synopsys VHDL Debugger window.
This will run the timing simulation test bench and display the simulation trace of your design.
Return to the UNIX environment by selecting EXECUTE-QUIT from the simulator menu.
If you need more information on timing simulation, see the “Simulating Your Design" chapter.
