Functional Simulation Using VSS

Functional simulation is used to debug your logic before fitting your design into a CPLD. The Xilinx CPLD Synopsys Interface fully supports functional simulation using the Synopsys VSS simulator, including all instantiated cells from the XC9000 library.

To prepare a test bench configuration for simulation, you must analyze each of the design and test bench source files in the proper bottom-up sequence.

The following procedure uses the stand-alone VHDL Analyzer (vhdlan) and the VHDL Debugger Simulator (vhdldbx).

1. Analyze your source CPLD design file. Enter the following UNIX command:
   
   vhdlan design_name.vhd
   
   For example:
   
   vhdlan scan.vhd
   
   
2. Analyze the test bench file. Enter the following UNIX command:
   
   vhdlan test_bench_name.vhd
   
   For example:
   
   vhdlan scan_tb.vhd
   
   
3. Invoke the Synopsys VSS Simulator. Enter the following UNIX command to invoke the VHDL debugger:
   
   vhdldbx
   
   

You are then prompted for a configuration name. Select the name of the configuration declared in the test_bench_name.vhd file. For example, for the scan design, select the following:

CFG_SCAN_TB

The vhdldbx selector window appears.

After you click OK, the vhdldbx user interface window appears.

To run your simulation, typically you first declare the signals you want to display in a trace window. For example, to display all signals appearing on the CPLD pins, you can enter the following vhdldbx command:

trace *'signal.

To run all the simulation vectors in your test bench, select the RUN command. A trace window will be displayed.

After functional simulation is successful, you are ready to implement your design and create the physical layout information required for timing simulation.

Design Implementation

After you have debugged your design using functional simulation, you can compile it using synthesis and implement it in a CPLD using the Xilinx fitter. Design implementation is a prerequisite for performing timing simulation.

You can use DC Shell or you can use the Synopsys graphic interface (Design Analyzer) to create the EDIF netlist file required by the Xilinx fitter. This gate-level netlist file consists of cells from the XC9000 library but does not contain timing information. The Xilinx fitter processes the netlist file and places the logical design into the physical architecture of a target CPLD.

After the design is implemented by the Xilinx fitter, the actual target device timing information is available for timing simulation.

The following steps show you an overview of the CPLD implementation procedure.

1. Analyze the source design file. This must be repeated in the synthesis environment (DC Shell); the results of vhdlan cannot be used for synthesis.
   
   
2. Compile the design, targeting the XC9000 library, and create a netlist.
   
   
3. Run the Xilinx fitter, using the cpld command or the Design Manager to process the netlist.
   
   

Usually, simulation is not repeated until after fitting when all actual timing results have been applied.

Examine the appropriate fitter report files to verify that the fitter completed successfully. You may wish to target a smaller device or add more functions to your design if there are remaining unused resources.

After design implementation, you are ready to prepare the timing model for timing simulation.

Preparing the Timing Simulation Model

From Command Line

The ngd2vhdl command translates the timing simulation database file (design_name.nga) produced by the cpld command into the required VHDL simulation output file(s).

If you prefer to create a PRLD input port and control it using your testbench, create your timing simulation model as follows:

ngd2vhdl design_name -w -gp design_name_time

If you prefer to use the automatic ROC cell to pulse the PRLD net, create your timing simulation model as follows:

ngd2vhdl design_name -w design_name_time

Invoking the ngd2vhdl command with no parameters produces a listing of all available command-line options.

The design_name is the name of the design as specified when running the cpld command, without path qualifiers and without extension.

The ngd2vhdl command produces a structural VHDL file (design_name_time.vhd) and an SDF-formatted timing back-annotation file (design_name_time.sdf), for use with the Synopsys VSS simulator or other VITAL-compatible simulator. A procedure for using the VSS simulator is described below.

Similarly, the ngd2ver command produces a structural Verilog HDL file (design_name_time.v) and an SDF-formatted timing back-annotation file (design_name_time.sdf).

The -gp option forces ngd2vhdl or ngd2ver to add a PRLD input port to the output VHDL or Verilog HDL file for CPLD designs. This allows the PRLD initialization signal to be stimulated as a top-level port by your test bench.

NOTE

When the fitter processes your design, some of your original nodes may be removed or replaced due to logic optimization. Such nodes cannot be viewed or stimulated during timing simulation. All of the device I/O port signals and register output signals are always maintained.

From Design Manager

1. Open the Options dialog box using one of the following methods.
   
   
   • If you haven`t yet performed design implementation, from the Design Manager menu, select Design Implement. Click on the Options button in the Implement dialog box.
     
     
   • If you have already completed implementation, select the revision, then go to the Flow Engine by selecting Tools Flow Engine. From the Flow Engine menu, select Setup Options.
     
     The Options dialog box appears.
     
     
2. In the Options dialog box, select the Produce Timing Simulation Data check box then select the Edit Template softkey.
   
   The Implementation Options template appears.
   
   
3. Select the Interface tab on the Implementation Options template.
   
   
4. Select VHDL or Verilog as the output format.
   
   
5. Click OK.
   
   When you implement the design, the Flow Engine produces timing simulation data files. Each time the data is produced, it is automatically exported to your design directory.
   
   

You can now use these files to simulate the design with a supported third party simulation tool.

Timing Simulation Using VSS

If you prepared your test bench as described earlier you can use the same test bench for timing simulation as used for functional simulation. By using the same test bench you can easily verify that the functionality of the device after mapping matches the functionality of your source design. You also eliminate any risk of errors from accidental differences between separate test bench files.

1. Analyze the timing simulation model produced by ngd2vhdl:
   
   vhdlan design_name_time.vhd
   
   For example:
   
   vhdlan scan_time.vhd
   
   
2. Analyze the test bench file name as used for functional simulation. Enter the following UNIX command:
   
   vhdlan test_bench_name.vhd
   
   For example:
   
   vhdlan scan_tb.vhd
   
   The simulation data base now contains the test bench design which interfaces to the chip through your source design entity read in step 1 but it contains the timing model architecture read in step 2.
   
   
3. Invoke the Synopsys VSS Simulator. Enter the following UNIX command:
   
   vhdldbx
   
   You are then prompted for the configuration named in the test_bench_name.vhd file. For example, for the scan design, select the following:
   
   CFG_SCAN_TB
   
   Before clicking "OK" you must specify the timing backannotation file information in the Arguments box.
   
   

All back-annotated timing in the .sdf file is applied to various instances within the design_name_time.vhd file. However, if you are simulating with a test bench, you must specify (to the simulator) the CPLD design instance to which you want to apply the back-annotated timing. It can then find all the referenced instances.

If you are using vhdldbx you need to specify two parameters:

• The sdf_top instance in the test bench configuration to which the back-annotated timing is applied:
  
  -sdf_top chip_instance_name
  
  For example:
  
  -sdf_top /scan_tb/UUT
  
  All back-annotated timing parameters in the .sdf file are applied relative to the chip instance.
  
  

• The file name of the .sdf backannotation timing file:
  
  -sdf design_name_time.sdf
  
  For example:
  
  -sdf scan_time.sdf
  
  

You can specify these parameters either in the dialog box which appears after invoking vhdldbx, or on the UNIX command line as you invoke vhdldbx.

The command line invocation format is:

vhdldbx -sdf_top chip_instance_name -sdf \ design_name_time.sdf configuration_name

For the scan design example, you should enter the following:

vhdldbx -sdf_top /scan_tb/UUT \

-sdf scan_time.sdf CFG_SCAN_TB

NOTE

If you use the -tb option of the ngd2vhdl command to create a testbench template file (.tvhd), all the instance names in the .sdf timing back-annotation file will be prefixed with “UUT/”. In this case, you would omit the instance name “/UUT” from your vhdldbx -sdf_top parameter. For example, if you prepared the scan design using the command:

ngd2vhdl -w -tb scan scan_time

then you would invoke the VSS simulator using the command:

vhdldbx -sdf_top /scan_tb -sdf scan_time.sdf \ CFG_SCAN_TB

Now you can run the same simulation vectors for timing simulation as you ran for functional simulation. However, in timing simulation, the registers are set to their initial states in response to the active-high pulse on PRLD.