Following the Design Flow

Creating FPGA and CPLD designs with Viewlogic tools involves the following steps.

1. Enter your design with the ViewDraw schematic editor or the ViewSynthesis VHDL compiler, making sure that you observe the Xilinx design requirements noted in this manual.
   
   
2. Test the functionality of your design by creating a functional simulation network (VSM file) and loading it into Digital Fusion to simulate the design. You can use ViewTrace to view the waveforms generated by the simulation.
   
   
3. Implement your FPGA or CPLD design using Xilinx Design Manager.
   
   
4. Verify the timing of your design by creating a timing simulation network (VSM file) and loading it into Digital Fusion to simulate the design. You can use ViewTrace to view the waveforms generated by the simulation.
   
   
5. Download the design to the Xilinx device and verify the board.
   
   

Refer to the following figure to see the Xilinx-Viewlogic design flow.

Figure 1.1 Xilinx-VIEWlogic Flow