Timing simulation verifies a placed and routed design by using worst-case routing and block delay information. The delay information extracts from the routed design and passes to the back-annotated simulation netlist for use during timing simulation. Timing simulation reduces the need for hardware debugging by determining whether or not the design works under worst-case conditions.
You can also use timing simulation to determine the device speed grade required for a particular application.
This chapter describes how to prepare a simulation network for a timing simulation in the Viewlogic simulation environment. It also describes how to load ViewTrace to view the simulation signals in a waveform format.
However, this chapter does not document specific Viewlogic commands for ViewSim, Speedwave, or ViewTrace. For information regarding the use of these tools, consult the online Viewlogic help files accessible from all of these tools.
This chapter contains these sections.
