Use a constraints file to supply constraints information in a textual form rather than putting it on a schematic (a method sometimes more efficient than putting constraints on a schematic). An example of a constraints file, the calc_4ke.ucf (supplied with this tutorial), appears in this section. The constraints file syntax is the same for all families.
You must instruct the place and route software to read and apply the .ucf file when the design reads into the Xilinx Design Manager.
net SWITCH7 LOC=p19;
net SWITCH6 LOC=p20;
net SWITCH5 LOC=p23;
net SWITCH4 LOC=p24;
net SWITCH3 LOC=p25;
net SWITCH2 LOC=p26;
net SWITCH1 LOC=p27;
net SWITCH0 LOC=p28;
net A LOC=p49;
net B LOC=p48;
net C LOC=p47;
net D LOC=p46;
net E LOC=p45;
net F LOC=p50;
net G LOC=p51;
net OFL LOC=p41;
net GAUGE3 LOC=p61;
net GAUGE2 LOC=p62;
net GAUGE1 LOC=p65;
net GAUGE0 LOC=p66;
net STACKLED3 LOC=p57;
net STACKLED2 LOC=p58;
net STACKLED1 LOC=p59;
# net STACKLED0 LOC=p60;
net NOTGBLRESET LOC=p56;
Because you only specified a pin location for one of the many inputs and outputs on the Calc schematic, you must use a constraints file to place the rest. The “Using the Xilinx Design Manager” section describes this procedure.
