PAR and the Timing Analysis Software

Timing-driven PAR is based upon Xilinx's timing analysis software, an integrated static timing analysis tool (that is, it does not depend on input stimulus to the circuit). This means that placement and routing are executed according to timing constraints that you specify in the beginning of the design process. The timing analysis software interacts with PAR to ensure that the timing constraints you impose on the design are met.

To use timing-driven PAR, you can specify your timing constraints in any of these ways.

• You can enter the timing constraints as properties in a schematic capture or HDL design entry program.
  
  
• You can write your timing constraints into a User Constraints File (UCF). This file is processed by NGDBuild when the logical design database is generated.
  
  To avoid manually entering timing constraints in a UCF file, use the Xilinx Constraints Editor, a tool that greatly simplifies constraint creation. For a detailed description of how to use the editor, see the Constraints Editor Guide.
  
  
• You can enter the timing constraints in the Physical Constraints File (PCF), a file that is generated by MAP. The PCF file contains any timing constraints specified using the two previously described methods and any additional constraints you enter directly in the file.
  
  

Timing-driven placement and timing-driven routing are automatically invoked if PAR finds timing constraints in the physical constraints file. The physical constraints file serves as input to the timing analysis software. The timing constraints supported by the Xilinx Development System are described in the “Using Timing Constraints” chapter.

Note: Depending upon the types of timing constraints specified and the values assigned to the constraints, PAR run time may be increased.

When PAR is complete, you can verify that the design's timing characteristics (relative to the physical constraints file) have been met by running TRACE (Timing Reporter and Circuit Evaluator), Xilinx's timing verification and reporting utility. TRACE, which is described in detail in the “TRACE” chapter, issues an ASCII report showing any timing warnings and errors and other information relevant to the design. There is a terse summary report of timing in the PAR report also.

Note: If you are going to run a design without timing constraints, better circuit performance most likely can be obtained by enabling the Delay Based Cleanup router pass. Alternatively, consider running timing driven PAR by supplying timing constraints with the input design.