Dedicated Global Signals in Back-Annotation Simulation

This section presents information on how global signals are treated in back-annotation simulation.

Note: For a description of the STARTUP and STARTUP_VIRTEX components, see the “Design Elements (SOP3 to XORCY_L)” chapter of the Libraries Guide.

XC3000A/L and 3100A/L

In XC3000 devices, the global reset signal (whose name varies depending on the CAE vendor) is assigned a pin on the device. You must include this pin in your call to the top level module and stimulate the pin. The global reset signal should be pulsed low to reset all flip-flops in the design, then held high for normal operation.

XC4000E/L, XC4000EX/XL/XV/XLA, and Spartan

For XC4000 and Spartan devices, a high signal on the GSR (Global Set/Reset) net initializes each flip-flop and latch to the state (0 or 1) specified by its INIT property (default is 0). A high signal on GTS (Global Tri-State) sets all outputs to a tristate condition. If you have not used the STARTUP component in your original design, these signals are initialized to their inactive states. Otherwise, you must stimulate the input GSR and GTS pins of the STARTUP device either directly or via logic from explicit pins on the device.

XC5200

In XC5200 devices, GR (Global Reset) is assigned a pin on the device. You must include this pin in your call to the top level module and stimulate the pin. The global reset signal is active-High. A high signal on GTS (Global Tri-State) sets all outputs to a tristate condition. If you have not used the STARTUP component in your original design, these signals are initialized to their inactive states. Otherwise, you must stimulate the input GR and GTS pins of the STARTUP device either directly or via logic from explicit pins on the device.

Virtex

For Xilinx Virtex devices, a high signal on the GSR (Global Set/Reset) net initializes each flip-flop and latch to the state (0 or 1) specified by its INIT property (default is 0) and Block RAM data outputs to 0. LUT RAM, Block RAM content, DLL, and SRL are not affected by GSR. A high signal on GTS (Global Tri-State) sets all outputs to a tristate condition. If you have not used the STARTUP_VIRTEX component in your original design, these signals are initialized to their inactive states. Otherwise, you must stimulate the input GSR and GTS pins of the STARTUP_VIRTEX device either directly or via logic from explicit pins on the device.