NGD2VHDL Notes

Following are notes on NGD2VHDL.

Bus Order in VHDL Files

When you compile your unit-under-test design from NGD2VHDL with your testbench, there may be mismatches on bused ports.

This problem occurs when your unit under test has top-level ports that are defined as LSB-to-MSB, as shown in the following example.

A: in STD_LOGIC_VECTOR (0 to 7);

As a result of the way your input design was converted to a netlist before it was read into the Xilinx implementation software, the Xilinx design database does not include information on how bus direction was defined in the original design. When NGD2VHDL writes out a structural timing VHDL description, all buses are written as MSB-to-LSB, as shown in the following example.

A: in STD_LOGIC_VECTOR (7 downto 0);

If your ports were defined as LSB-to-MSB in your original input design and testbench, there is a port mismatch when the testbench is compiled for timing simulation. Use one of the following to solve this problem.

• In the testbench, modify the instantiation of the unit under test so that all ports are defined as MSB-to-LSB for timing simulation
  
  
• Define all ports as MSB-to-LSB in the original design and testbench, by using the downto clause instead of the to clause to specify a bus range.
  
  

Note: Bus order will be preserved if the design input file is EDIF and the buses are declared as port arrays, if you are doing logical simulation, or if you are doing back-annotation with an NGM file as input.

VHDL Identifier Naming Conventions

An identifier in a VHDL file must adhere to the following conventions. For more information see the IEEE Standard VHDL Language Reference Manual or the IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification.

• Must begin with alphabetic characters (a-z or A-Z)
  
  
• Can contain the characters a-z, A-Z, 0-9, or _
  
  
• Can be up to 1024 characters long
  
  
• Cannot contain white space
  
  

Note: Identifiers are not case sensitive.

During the name legalization process, NGD2VHDL substitutes any illegal characters with the underscore (_) character.

Compile Scripts for VHDL Libraries

You must compile libraries for your simulation tools to recognize Xilinx components. To perform timing or post-synthesis functional HDL simulation, you must compile the SimPrim libraries. If the HDL code contains instantiated components, you must compile the UniSim or LogiBLOX libraries. If the HDL code contains instantiated components from the CORE Generator System, you must compile the COREGen behavioral models before you can perform a behavioral simulation. Refer to the CORE Generator System User Guide for more information.

To get the necessary compile scripts for ModelSim VHDL, go to http://support.xilinx.com/techdocs/1923.htm.