Partlist.xct File Contents

The partlist.xct file contains detailed information about architectures and devices.

The partlist.xct file is a series of part entries. There is one entry for every part supported in the installed software. The following subsections describe the information contained in the partlist.xct file.

Header

The first part is a header for the entry. The format of the entry looks like the following.

part architecture family partname diename packagefilename

Following is an example for the XC4036EXhq240.

part4000 4036EXhq240 NA.die 4036hq240.pkg

Device Attributes

The header is followed by a list of device attributes. Not all attributes are applicable to all devices.

• BSCAN pin mappings: TDK=PAD# TDI=PAD# TMS=PAD#
  
  
• CLB row and column sizes: NCLBROWS=# NCLBCOLS=#
  
  
• Sub-family designation: STYLE=sub_family
  (For example, STYLE = XC4000EX)
  
  
• Width of the edge decoder (found in the XC5200 and XC4000 families): EDGE_DECODER=#
  
  
• Input registers: IN_FF_PER_IOB=#
  
  
• Output registers: OUT_FF_PER_IOB=#
  
  
• Number of pads per row and per column: NPADS_PER_ROW=# NPADS_PER_COL=#
  
  
• Bitstream information:
  
  
  • Number of frames: NFRAMES=#
    
    
  • Number bits/frame: NBITSPERFRAME=#
    
    

The preceding bulleted items display for both the -p and -v options. The following bulleted items only display when using the -v option.

• Number of IOBS in device: NIOBS=#
  
  
• Number of bonded IOBS: NBIOBS=#
  
  
• Slices per CLB: SLICES_PER_CLB=#
  
  For slice-based architectures; for example. virtex.
  
  (For non-slice based architectures, assume one slice per CLB)
  
  
• Flip-flops for each slice: FFS_PER_SLICE=#
  
  
• Latches for each slice: LATCHES_PER_SLICE={TRUE|FALSE}
  
  
• LUTs in a slice: LUT_NAME=name LUT_SIZE=#
  
  
• Number of global buffers: NUM_GLOBAL_BUFFERS=#
  
  (The number of places where a buffer can drive a global clock combination)
  
  
• External Clock IOB pins:
  
  
  • For the XC3000 family: TCLKIOB=PAD# BCLKIOB=PAD#
    
    
  • For the XC4000/XC4000E family:
    
    BUFGP_TL=PAD#, BUFGP_BL=PAD#,
    BUFGP_BR=PAD#, BUFGP_TR=PAD#,
    BUFGS_TL=PAD#, BUFGS_BL=PAD#,
    BUFGS_BR=PAD#, BUFGS_TR=PAD#
    
    
  • For the XC4000EX/XC4000XL/XC4000XLA/XC4000XV/SpartanXL families:
    
    BUFGLS_NNW=PAD#,
    BUFGLS_WNW=PAD#,
    BUFGLS_NNE=PAD#,
    BUFGLS_ENE=PAD#,
    BUFGLS_SSW=PAD#,
    BUFGLS_WSW=PAD#,
    BUFGLS_SSE=PAD#,
    BUFGLS_ESE=PAD#
    
    
  • For the XC5200 family:
    
    BUFG_TL=PAD#, BUFG_TR=PAD#,
    BUFG_BL=PAD#, BUFG_BR=PAD#
    
    
  • For the Virtex families:
    
    GCLKBUF0=PAD#, GCLKBUF1=PAD#,
    GCLKBUF2=PAD#, GCLKBUF3=PAD#
    
    
• Oscillator pins for the XC3000 family:
  OSCIOB1=PAD#, OSCIOB2=PAD#
  
  
• Block RAM:
  
  NUM_BLK_RAMS=# BLK_RAM_SIZE=#X#
  
  

(for example, NUM_BLK_RAMS=10 BLK_RAM_SIZE=4096X1)

• Select RAM:
  
  NUM_SEL_RAMS=#   SEL_RAM_SIZE=#X#
  
  
• Select Dual Port RAM:
  
  SEL_DP_RAM={TRUE|FALSE}
  
  This field indicates whether the select RAM can be used as a dual port ram. The assumption is that the number of addressable elements is reduced by half, that is, the size of the select RAM in Dual Port Mode is half that indicated by SEL_RAM_SIZE.
  
  
• Speed grade information: SPEEDGRADE=#
  
  
• Typical delay across a LUT for each speed grade: LUTDELAY=#
  
  
• Typical IOB input delay: IOB_IN_DELAY=#
  
  
• Typical IOB output delay: IOB_OUT_DELAY=#
  
  
• Maximum LUT constructed in a slice:
  
  MAX_LUT_PER_SLICE=#
  
  (From all the LUTs in the slice)
  
  
• Max LUT constructed in a CLB: MAX_LUT_PER_CLB=#
  
  (This field describes how wide a LUT can be constructed in the CLB from the available LUTs in the slice.)
  
  
• Number of internal tristate buffers in a device: NUM_TBUFFS=#