|
|
|
|
|
A clock period specification checks timing clocked by the net (all paths that terminate at a register clocked by the specified net).
The period specification is attached to the clock net. The definition of a clock period is unlike a FROM-TO style specification because the timing analysis tools automatically take into account any inversions of the clock net at register clock pins.
A PERIOD constraint on the clock net in the following figure would generate a check for delays on all paths that terminate at a pin that has a setup or hold timing constraint relative to the clock net. This could include the data paths D1 to CLB1.D, CLB1.Q to CLB2.D, as well as the path EN to CLB2.EC (if the enable were synchronous with respect to the clock).
Figure 6.10 Paths for PERIOD ConstraintIn 2.1i, the timing tool no longer checks pad-to-register paths relative to setup requirements. For example in the preceding figure, the path from D1 to Pin D of CLB1 is no longer included in the PERIOD constraint.
A simple method of defining a clock period is to attach the following attribute directly to a net in the path that drives the register clock pins.
Schematic syntax
PERIOD = period { HIGH | LOW } [high_or_low_time]
UCF syntax
[period_item] PERIOD = period { HIGH | LOW } [high_or_low_time];
period_item is one of the following,
period is the required clock period. The default units are nanoseconds, but the timing number can be followed by ps, ns, us, or ms. Units may be entered with or without a leading space, and are case-insensitive. The HIGH|LOW keyword indicates whether the first pulse in the period is high or low, and the optional high_or_low_time is the duty cycle of the first pulse. If an actual time is specified, it must be less than the period. If no high or low time is specified the default duty cycle is 50%. The default units for high_or_low_time is ns, but the number can be followed by % or by ps, ns, us or ms if you want to specify an actual time measurement.
The PERIOD constraint is forward traced in exactly the same way a TNM would be and attaches itself to all of the flip-flops that the forward tracing reaches. If a more complex form of tracing behavior is required (for example, where gated clocks are used in the design), you must place the PERIOD on a particular net or use the preferred method described next.
The preferred method for defining a clock period allows more complex derivative relationships to be defined as well as a simple clock period. The following attribute is attached to a TIMESPEC symbol in conjunction with a TNM attribute attached to the relevant clock net.
Schematic syntax in a TIMSPEC symbol
TSidentifier=PERIOD TNM_reference period {HIGH | LOW} [high_or_low_time]
UCF syntax
TIMESPEC TSidentifier=PERIOD TNM_reference period {HIGH | LOW} [high_or_low_time];
identifier is a reference identifier that has a unique name.
TNM_reference is the identifier name that is attached to a clock net (or a net in the clock path) using a TNM attribute.
The variable name period is the required clock period. The default units for period are nanoseconds, but the number can be followed by ps, ns, us, or ms. Units may be entered with or without a leading space, and are case-insensitive. The HIGH|LOW keyword indicates whether the first pulse in the period is high or low, and the optional high_or_low_time is the polarity of the first pulse. If an actual time is specified, it must be less than the period. If no high or low time is specified the default duty cycle is 50%. The default units for high_or_low_time is ns, but the number can be followed by % or by ps, ns, us, or ms if you want to specify an actual time measurement.
Example
Clock net sys_clk has the attribute tnm=master_clk attached to it and the following attribute is attached to a TIMESPEC primitive.
Schematic syntax in a TIMESPEC symbol
TS_master=PERIOD master_clk 50 HIGH 30
UCF syntax
TIMESPEC TS_master=PERIOD master_clk 50 HIGH 30;
This period constraint applies to the net master_clk, and defines a clock period of 50 nanoseconds, with an initial 30 nanosecond high time.
The preferred method of defining a clock period uses an identifier, allowing another clock period specification to reference it. To define the relationship in the case of a derived clock, use the following syntax.
Schematic syntax in a TIMSPEC symbol
TSidentifier=PERIOD TNM_reference another_PERIOD_identifier
[{/|*}number] [{HIGH|LOW} high_or_low_time]
UCF syntax
TIMESPEC TSidentifier=PERIOD TNM_reference another_PERIOD_identifier
[{/|*}number] [{HIGH|LOW} high_or_low_time];
Example
A clock net has the attribute tnm=slave_clk attached to it and the following attribute is attached to a TIMESPEC primitive.
Schematic syntax in a TIMESPEC symbol
ts_slave1=PERIOD slave_clk TS_master *4
UCF syntax
TIMESPEC ts_slave1=PERIOD slave_clk TS_master *4;
A TNM or TNM_NET group on a net is usually traced forward to tag all of the flip-flops, latches, and RAMs driven by that net. However, if the group traces into the clock input pin of a Virtex or Spartan2 CLKDLL or CLKDLLHF symbol, it is not simply traced through the CLKDLL outputs.
When a TNM or TNM_NET group is traced into the CLKIN pin of a Virtex CLKDLL component, NGDBuild examines the TNM group to ensure that it meets all the following conditions.
Note: If a group is traced into the CLKDLL but is not used in exactly one PERIOD specification, NGDBuild issues an error. To tag the elements driven by the CLKDLL, place TNM or TNM_NET groups directly on the CLKDLL output nets.
If the TNM or TNM_NET group meets these conditions, NGDBuild copies the PERIOD specification to each CLKDLL output net and adjusts it as shown in the following table.
| Output Pin | Adjustments |
|---|---|
| CLK0 CLK90 CLK180 CLK270 | If the DUTY_CYCLE_CORRECTION=TRUE property is found, the duty cycle is adjusted to 50%/50%. If DUTY_CYCLE_CORRECTION=FALSE is found, the duty cycle is unchanged from the original PERIOD specification. If the DUTY_CYCLE_CORRECTION property is not found, the default value of TRUE is assumed. |
| CLK2X | If originally expressed as FREQUENCY, the FREQUENCY value is doubled. If originally expressed as PERIOD, the PERIOD value is divided in half. The duty cycle is adjusted to 50%/50%. |
| CLKDV | If originally expressed as FREQUENCY, the FREQUENCY value is divided by the value in the CLKDV_DIVIDE property. If originally expressed as PERIOD, the PERIOD value is multiplied by the value in the CLKDV_DIVIDE property. If the CLKDV_DIVIDE value is not found, the default value of 2.0 is used. The duty cycle is adjusted to 50%. |
In addition to creating new PERIOD specifications at the CLKDLL outputs, NGDBuild also creates new TNM or TNM_NET groups to use in those specifications. The new groups are traced forward from the CLKDLL output net to tag all flip-flops, latches, and RAMs controlled by that clock signal.
Each new TNM or TNM_NET group created by NGDBuild is named the same as the corresponding CLKDLL output net.The TSidentifier for the new PERIOD specification uses the TS_ prefix followed by the net name. These new groups and specifications are shown in timing analysis reports.
The following figure indicates how new groups are created at the outputs of the DLL for a TNM_NET group specification at the CLKDLL inputs.
The sample PERIOD specification for the figure is as follows:
TIMESPEC TS01=PERIOD CLK1 10 HIGH 3ns
Figure 6.11 TNM_NET GenerationNote: The new TNM or TNM_NET groups and PERIOD specifications are not visible in the Constraints Editor, because they are created from the user-applied specification each time NGDBuild is run.