The Logical DRC

The Logical DRC (Design Rule Check), is a series of tests run to verify the logical design in the NGD (Generic Database) file. The Logical DRC (also called the NGD DRC) performs device-independent checks; they do not depend on the FPGA to which you will eventually map the design.

The Logical DRC generates messages to show the status of the tests performed. Messages can be error messages (for conditions where the logic will not operate correctly) or warnings (for conditions where the logic is incomplete).

The Logical DRC runs automatically at these times.

• At the end of NGDBuild, before NGDBuild writes out the NGD file. NGDBuild writes out the NGD file if DRC warnings are discovered, but does not write out an NGD file if DRC errors are discovered.
  
  
• At the end of each netlist writer (NGD2EDIF, NGD2VER, or NGD2VHDL), before writing out the netlist file. The netlist writers do not perform the entire DRC; they only perform a subset of the DRC tests. A netlist writer writes out a netlist file even if DRC warnings or errors are discovered.