The MAP Process

To map a design, MAP performs these steps.

1. Choose the target Xilinx device, package, and speed. MAP selects a part in this way.
   
   
   • If a part is specified on the MAP command line, this is the part used.
     
     
   • If the command line does not specify a part, MAP selects the part specified in the input NGD file. If the information in the input NGD file does not specify a complete architecture, device, and package, you receive an error message and MAP does not continue. MAP supplies a default speed if necessary.
     
     
2. Read the information in the input design file.
   
   
3. Perform a Logical DRC (Design Rule Check) on the input design. If any DRC errors are detected, the MAP run is aborted. If any DRC warnings are detected, the warnings are reported, but the MAP run continues. The Logical DRC (also called the NGD DRC) is described in “The Logical Design Rule Check” chapter.
   
   

   Note: Step 3 is skipped if the NGDBuild DRC was successful.

4. Assign the device global clock buffers (if possible).
   
   
5. Remove unused logic. All unused components and nets are removed, unless these conditions exist.
   
   
   • A Xilinx S (Save) constraint has been placed on a net during design entry. If an unused net has an S constraint, the net and all used logic connected to the net (as drivers or loads) is retained. All unused logic connected to the net is deleted.
     For a more complete description of the S constraint, see the “Attributes, Constraints, and Carry Logic” chapter of the Libraries Guide.
     
     
   • The -u option was specified on the MAP command line. If this option is specified, all unused logic is kept in the design.
     
     
6. Map pads and their associated logic into IOBs.
   
   
7. Map the logic into Xilinx components (IOBs, CLBs, etc.). If any Xilinx mapping control symbols appear in the design hierarchy of the input file (for example, FMAP or HMAP symbols targeted to an XC4000EX device), MAP uses the existing mapping of these components in preference to remapping them. The mapping is influenced by various constraints; these constraints are described in the “Attributes, Constraints, and Carry Logic” chapter of the Libraries Guide.
   
   
8. Update the information received from the input NGD file and write this updated information into an NGM file. This NGM file contains both logical information about the design and physical information about how the design was mapped. The NGM file is used only for back-annotation.
   
   
9. Create a physical constraints (PCF) file. This is a text file containing any constraints specified during design entry. If no constraints were specified during design entry, an empty file is created so that you can enter constraints directly into the file using a text editor or indirectly through the FPGA Editor.
   
   MAP either creates a PCF file if none exists or rewrites an existing file by overwriting the schematic-generated section of the file (between the statements SCHEMATIC START and SCHEMATIC END). For an existing constraints file, MAP also checks the user-generated section and may either comment out constraints with errors or halt the program. If no errors are found in the user-generated section, the section remains the same.
   
   
10. Create an MDF file, which describes how logic was decomposed when the design was mapped. The MDF file is used for guided mapping.
    
    This step does not apply to Virtex or Spartan2.
    
    
11. Run a physical Design Rule Check (DRC) on the mapped design. If DRC errors are found, MAP does not write an NCD file.
    
    
12. Create an NCD file, which represents the physical design. The NCD file describes the design in terms of Xilinx components - CLBs, IOBs, etc.
    
    
13. Write a MAP report (MRP) file, which lists any errors or warnings found in the design, details how the design was mapped, and supplies statistics about component usage in the mapped design.