Simulating Map Results

When simulating from NGM files, you are not simulating a mapped result, that is, you are simulating the logical circuit description. Simulating from the NCD file actually simulates the physical circuit description.

MAP may generate an error that is not detected in the back-annotated simulation netlist. For example, you may run the following command after running MAP to generate the backannotated simulation netlist.

ngdanno mapped.ncd mapped.ngm -o mapped.nga

This command creates a back-annotated simulation netlist using the logical-to-physical cross-reference file named mapped.ngm. This cross-reference file contains information about the logical design netlist which means that the back-annotated simulation netlist (mapped.nga) is actually a back-annotated version of the logical design. However, if MAP makes a physical error, for example, implements an Active Low function for an Active High function, this error will not be detected in the mapped.nga file which means that the error will not show up in the simulation.

Consider the following logical circuit generated by NGBuild from an input design file.

Figure 8.4 Logical Circuit Representation

Note the Boolean output from the combinatorial logic. Suppose that after running MAP for the preceding circuit, you obtain the following result.

Figure 8.5 CLB Configuration

Note that MAP has generated an active low (C) instead of an active high (C). Therefore, the Boolean output for the combinatorial logic is incorrect. When you run NGDAnno using the mapped.ngm file (ngdanno mapped.ncd mapped.ngm -o mapped.nga), you will not detect this logical error because the delays are back-annotated to the correct logical design not to the physical design.

One way to detect the error is by running the NGDAnno command without using the mapped.ngm cross-reference file.

ngdanno mapped.ncd -o mapped.nga

Then physical simulations using the mapped.nga file will normally detect a physical error. However, even though, an error is detected, the specific type of error is not easily recognizable. You can use the FPGA Editor to try to pinpoint the error or call Xilinx Customer Support. It is also possible that the physical simulation is reporting an error that does not exist, that is, the CLB configuration is correct. In that instance, you can use the FPGA Editor to determine if the CLB is correctly modelled.

Lastly, if both the logical and physical simulations do not discover existing errors, you may need to use more test vectors in the simulations.