Design Flow

The following steps provide an overview of the FPGA Editor design flow.

1. Enter your design using a schematic design tool or HDL (Hardware Description Language).
   
   
2. Save your design in EDIF (Electronic Data Interchange Format).
   
   
3. Run NGDBuild, which creates an NGD (Native Generic Database) file.
   
   
4. Run the MAP program, which creates an NCD (Native Circuit Description) file.
   
   
5. Load your design into the FPGA Editor, make necessary changes, and save the modified design as an NCD file.
   
   
6. Run the PAR (Place and Route) program on the modified NCD file.
   
   

The following figure shows the complete Xilinx design flow, including editing your design in the FPGA Editor.

Figure 1.1 Design Flow