LogiBLOX Guide
Appendix A
LogiBLOX Versus X-BLOX/Memgen
LogiBLOX is a superset of both X-BLOX™ and Memgen. For an HDL flow, the methodology is the same; LogiBLOX generates the HDL template to instantiate a module.
For a schematic design flow, the LogiBLOX design rules are much simpler than the X-BLOX design rules:
- Bus size: In an X-BLOX design, data type and bus width of a module can be specified at a single point in a data path. During module expansion, X-BLOX propagates the information through the entire data path.
Each LogiBLOX symbol is already sized with the bus_width attribute. The results of this difference are:
- BUS_DEF, CAST, SLICE, ELEMENT, and BUS_IFnn are no longer needed on a LogiBLOX schematic. The bus_width and encoding of the LogiBLOX module are implicitly defined.
- The bus connected to the LogiBLOX symbol should be labeled with size information as a standard schematic bus, that is, Datain[7:0] in Viewlogic. One of the main benefits of a sized module is that data propagation during module expansion is eliminated, which decreases the LogiBLOX implementation run time.
- The differences between the .mem file of LogiBLOX and the .mem file of Memgen or of the PROM, SRAM, and DPRAM symbols are as follows:
- The LogiBLOX memfile does not allow PART declaration.
- The radix of data section is determined by the RADIX command. It cannot be overridden by 2#1101#, for example.
- '#' and '_' are disallowed.
- The depth value should be a multiple of 16; the maximum value is 256.
- X-BLOX can perform global design optimization such as implementing flip-flops in IOBs and inserting global buffers. This process, which was run-time consuming, is bypassed in LogiBLOX. (The MAP program has the ability to perform this optimization.) One of the consequences is the X-BLOX Inputs, Outputs and Bidir_IO symbols are replaced by LogiBLOX PAD and I/O modules. The replacement allows you to address a complex IO configuration.
- The symbol attributes are mostly identical for both LogiBLOX and X-BLOX. Some have changed such as:
LOC[0] = P19, LOC[1]=P20
becomes
PAD_LOC = 0:P19.1:P20
The constraints (L, LT, TL, T, TR, RT, R, RB, BR, B, BL, LB) are no longer valid for the I/O modules.