SR4CLED, SR8CLED, SR16CLED

4-, 8-, 16-Bit Shift Registers with Clock Enable and Asynchronous Clear

SR4CLED, SR8CLED, and SR16CLED are 4-, 8-, and 16-bit shift registers, respectively, with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D), and four control inputs: clock enable (CE), load enable (L), shift left/right (LEFT), and asynchronous clear (CLR). The register ignores clock transitions when CE and L are Low. The asynchronous clear, when High, overrides all other inputs and resets the data outputs (Qn) Low. When L is High and CLR is Low, the data on the D inputs is loaded into the corresponding Q bits of the register. When CE is High and L and CLR are Low, data is shifted right or left, depending on the state of the LEFT input. If LEFT is High, data on the SLI is loaded into Q0 during the Low-to-High clock transition and shifted left (to Q1, Q2, and so forth) during subsequent clock transitions. If LEFT is Low, data on the SRI is loaded into the last Q output (Q3 for SR4CLED, Q7 for SR8CLED, or Q15 for SR16CLED) during the Low-to-High clock transition and shifted right (to Q2, Q1,... for SR4CLED; to Q6, Q5,... for SR8CLED; and to Q14, Q13,... for SR16CLED) during subsequent clock transitions. The truth tables for SR4CLED, SR8CLED, and SR16CLED indicate the state of the Q outputs under all input conditions for SR4CLED, SR8CLED, and SR16CLED.

The register is asynchronously cleared, outputs Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.

Table 10_1 SR4CLED Truth Table

Inputs								Outputs
CLR	L	CE	LEFT	SLI	SRI	D3 - D0	C	Q0	Q3	Q2 - Q1
1	X	X	X	X	X	X	X	0	0	0
0	1	X	X	X	X	D3- D0		d0	d3	dn
0	0	0	X	X	X	X	X	No Chg	No Chg	No Chg
0	0	1	1	SLI	X	X		SLI	q2	qn-1
0	0	1	0	X	SRI	X		q1	SRI	qn+1
dn = state of referenced input one setup time prior to active clock transition qn-1 and qn+1 = state of referenced output one setup time prior to active clock transition

Table 10_2 SR8CLED Truth Table

Inputs								Outputs
CLR	L	CE	LEFT	SLI	SRI	D7 - D0	C	Q0	Q7	Q6 - Q1
1	X	X	X	X	X	X	X	0	0	0
0	1	X	X	X	X	D7 - D0		d0	d7	dn
0	0	0	X	X	X	X	X	No Chg	No Chg	No Chg
0	0	1	1	SLI	X	X		SLI	q6	qn-1
0	0	1	0	X	SRI	X		q1	SRI	qn+1
dn = state of referenced input one setup time prior to active clock transition qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

Table 10_3 SR16CLED Truth Table

Inputs								Outputs
CLR	L	CE	LEFT	SLI	SRI	D15 - D0	C	Q0	Q15	Q14 - Q1
1	X	X	X	X	X	X	X	0	0	0
0	1	X	X	X	X	D15 - D0		d0	d15	dn
0	0	0	X	X	X	X	X	No Chg	No Chg	No Chg
0	0	1	1	SLI	X	X		SLI	q14	qn-1
0	0	1	0	X	SRI	X		q1	SRI	qn+1
dn = state of referenced input one setup time prior to active clock transition qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

Figure 10.6 SR8CLED Implementation XC3000, XC4000E, XC4000X, XC5200, Spartan, SpartanXL, Spartan2, Virtex

Figure 10.7 SR8CLED Implementation XC9000