X74_161

4-Bit Binary Counter with Parallel and Trickle Enables, Active-Low Load Enable, and Asynchronous Clear

X74_161 is a 4-stage, 4-bit, synchronous, loadable, resettable, cascadable binary counter. The active-Low asynchronous clear (CLR), when Low, overrides all other inputs and resets the data outputs (QD, QC, QB, QA) and the ripple carry-out output (RCO) Low. When the active-Low load enable (LOAD) is Low and CLR is High, parallel clock enable (ENP) and trickle clock enable (ENT) are overridden and the data on inputs A, B, C, and D is loaded into the counter during the Low-to-High clock (CK) transition. The data outputs (QD, QC, QB, QA) increment when LOAD, ENP, ENT, and CLR are High during the Low-to-High clock transition. The counter ignores clock transitions when LOAD is High and ENP or ENT are Low. RCO is High when QD - QA and ENT are High.

The carry-lookahead design accommodates large counters without extra gating. Refer to “Carry-Lookahead Design” in the “X74_160” section for more information.

Inputs						Outputs
CLR	LOAD	ENP	ENT	D - A	CK	QD - QA	RCO
0	X	X	X	X	X	0	0
1	0	X	X	D - A		d - a	RCO
1	1	0	X	X	X	No Chg	RCO
1	1	X	0	X	X	No Chg	0
1	1	1	1	X		Inc	RCO
RCO = (QD•QC•QB•QA•ENT) d - a = state of referenced input one setup time prior to active clock transition

Figure 11.19 X74_161 Implementation XC3000, XC4000E, XC4000X, XC5200, Spartan, SpartanXL

Figure 11.20 X74_161 Implementation XC9000