CC8RE, CC16RE

8-, 16-Bit Cascadable Binary Counters with Clock Enable and Synchronous Reset

CC8RE and CC16RE are, respectively, 8- and 16-bit (stage), synchronous, resettable, cascadable binary counters. These counters are implemented using carry logic with relative location constraints to ensure efficient placement of logic. The synchronous reset (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs and CE are High.

Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(t_CE-TC), where n is the number of stages and the time t_CE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not.

The counter is asynchronously cleared, with Low outputs, when power is applied. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR (XC5200) and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.

Inputs			Outputs
R	CE	C	Qz - Q0	TC	CEO
1	X		0	0	0
0	0	X	No Chg	No Chg	0
0	1		Inc	TC	CEO
z = 7 for CC8RE; z = 15 for CC16RE TC = Qz•Q(z-1)•Q(z-2)•...•Q0•CE CEO = TC•CE

Topology for XC4000, Spartan, SpartanXL

This is the CC8RE (8-bit) and CC16RE (16-bit) topology for XC4000E, XC4000X, Spartan, and SpartanXL devices.

In the process of combining the logic that loads CEO and TC, the place and route software might map the logic that generates CEO and TC to different function generators. If this mapping occurs, the CEO and TC logic cannot be placed in the uppermost CLB as indicated in the illustration.

Topology for XC5200

This is the CC8RE (8-bit) and CC16RE (16-bit) topology for XC5200 devices.

Figure 4.27 CC8RE Implementation XC4000E, XC4000X, Spartan, SpartanXL

Figure 4.28 CC8RE Implementation XC5200

Figure 4.29 CC8RE Implementation Spartan2, Virtex