CJ4RE, CJ5RE, CJ8RE

4-, 5-, 8-Bit Johnson Counters with Clock Enable and Synchronous Reset

CJ4RE, CJ5RE, and CJ8RE are resettable Johnson/shift counters. The synchronous reset (R) input, when High, overrides all other inputs and causes the data (Q) outputs to go to logic level zero during the Low-to-High clock (C) transition. The counter increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE) is High during the Low-to-High clock transition. Clock transitions are ignored when CE is Low.

For CJ4RE, the Q3 output is inverted and fed back to input Q0 to provide continuous counting operation. For CJ5RE, the Q4 output is inverted and fed back to input Q0. For CJ8RE, the Q7 output is inverted and fed back to input Q0.

The counter is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.

Table 4_4 CJ4RE Truth Table

Inputs			Outputs
R	CE	C	Q0	Q1	Q2	Q3
1	X		0	0	0	0
0	0	X	No Chg	No Chg	No Chg	No Chg
0	1		!q3	q0	q1	q2
q = state of referenced output one setup time prior to active clock transition

Table 4_5 CJ5RE Truth Table

Inputs			Outputs
R	CE	C	Q0	Q1	Q2	Q3	Q4
1	X		0	0	0	0	0
0	0	X	No Chg	No Chg	No Chg	No Chg	No Chg
0	1		!q4	q0	q1	q2	q3
q = state of referenced output one setup time prior to active clock transition

Table 4_6 CJ8RE Truth Table

Inputs			Outputs
R	CE	C	Q0	Q1 - Q7
1	X		0	0
0	0	X	No Chg	No Chg
0	1		!q7	q0 - q6
q = state of referenced output one setup time prior to active clock transition

Figure 4.40 CJ8RE Implementation XC3000, XC4000E, XC4000X, XC5200, XC9000, Spartan, SpartanXL, Spartan2, Virtex