CAPTURE_VIRTEX

Virtex Register State Capture for Bitstream Readback

CAPTURE_VIRTEX provides user control over when to capture register (flip-flop and latch) information for readback. Virtex devices provide the readback function through dedicated configuration port instructions, instead of with a READBACK component as in other FPGA architectures. The CAPTURE_VIRTEX symbol is optional. Without it readback is still performed, but the asynchronous capture function it provides for register states is not available.

Note: Virtex only allows for capturing register (flip-flop and latch) states. Although LUT RAM, SRL, and block RAM states are read back, they cannot be captured.

An asserted High CAP signal indicates that the registers in the device are to be captured at the next Low-to-High clock transition. The Low-to-High clock transition triggers the capture clock (CLK) which clocks out the readback data.

By default, data is captured after every trigger (transition on CLK while CAP is asserted). To limit the readback operation to a single data capture, you can add the ONESHOT attribute to CAPTURE_VIRTEX. Refer to the “ONESHOT” section of the “Attributes, Constraints, and Carry Logic” chapter for information on the ONESHOT attribute.

For details on the Virtex readback functions, refer to the Virtex datasheets on the Xilinx web site, http://support.xilinx.com.