CB2CLED, CB4CLED, CB8CLED, CB16CLED

2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear

CB2CLED, CB4CLED, CB8CLED, and CB16CLED are, respectively, 2-, 4-, 8- and 16-bit (stage), synchronously loadable, asynchronously clearable, cascadable, bidirectional binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High and UP is Low during the Low-to-High clock transition. The Q outputs increment when CE and UP are High. The counter ignores clock transitions when CE is Low.

For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TC output is High when all Q outputs and UP are Low. To cascade counters, the CEO output of each counter is connected to the CE pin of the next stage. The clock, UP, L, and CLR inputs are connected in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(t_CE-TC), where n is the number of stages and the time t_CE-TC is the CE-to-TC propagation delay of each stage.

When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. For CPLD designs, refer to the “CB2X1, CB4X1, CB8X1, CB16X1” section for high-performance cascadable, bidirectional counters.

The counter is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted with an inverter in front of the GR/GSR input of STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX.

Inputs						Outputs
CLR	L	CE	C	UP	Dz - D0	Qz - Q0	TC	CEO
1	X	X	X	X	X	0	0	0
0	1	X		X	Dn	dn	TC	CEO
0	0	0	X	X	X	No Chg	No Chg	0
0	0	1		1	X	Inc	TC	CEO
0	0	1		0	X	Dec	TC	CEO
z = 1 for CB2CLED; z = 3 for CB4CLED; z = 7 for CB8CLED; z = 15 for CB16CLED dn = state of referenced input (Dn), one setup time prior to active clock transition TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (!Qz•!Q(z-1)•!Q(z-2)•...•!Q0•!UP) CEO = TC•CE

Figure 4.8 CB8CLED Implementation XC3000

Figure 4.9 CB8CLED Implementation XC4000E, XC4000X, XC5200, Spartan, SpartanXL, Spartan2, Virtex

Figure 4.10 CB4CLED Implementation XC9000