Libraries GuideChapter 5: Design Elements (F5MAP to FTSRLE)
FDCP
D Flip-Flop Asynchronous Preset and Clear
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Spartan2
| Virtex
|
|---|
N/A
| N/A
| N/A
| N/A
| Primitive
| N/A
| N/A
| Primitive
| Primitive
|
FDCP is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low on the Low-to-High clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Virtex and Spartan2 simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2 or STARTUP_VIRTEX symbol.
Inputs
| Outputs
|
|---|
CLR
| PRE
| D
| C
| Q
|
|---|
1
| X
| X
| X
| 0
|
0
| 1
| X
| X
| 1
|
0
| 0
| 0
| 
| 0
|
0
| 0
| 1
|
| 1
|
