Libraries GuideChapter 5: Design Elements (F5MAP to FTSRLE)
FDCPE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset and Clear
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Spartan2
| Virtex
|
|---|
N/A
| N/A
| N/A
| N/A
| N/A
| N/A
| N/A
| Primitive
| Primitive
|
FDCPE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the High-to-Low clock (C) transition. When CE is Low, the clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex and Spartan2 simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2 or STARTUP_VIRTEX symbol.
Inputs
| Outputs
|
|---|
CLR
| PRE
| CE
| D
| C
| Q
|
|---|
1
| X
| X
| X
| X
| 0
|
0
| 1
| X
| X
| X
| 1
|
0
| 0
| 0
| X
| X
| No Chg
|
0
| 0
| 1
| 0
| 
| 0
|
0
| 0
| 1
| 1
|
| 1
|
