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Libraries Guide
Chapter 5: Design Elements (F5MAP to FTSRLE)

FDRS_1

D Flip-Flop with Negative-Clock Edge and Synchronous Reset and Set

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Spartan2
Virtex
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Primitive
Primitive

FDRS_1 is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low during the High-to-Low clock (C) transition. (Reset has precedence over Set.) When S is High and R is Low, the flip-flop is set, output High, during the High-to-Low clock transition. When R and S are Low, data on the (D) input is loaded into the flip-flop during the High-to-Low clock transition.

The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex and Spartan2 simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2 or STARTUP_VIRTEX symbol.

Inputs
Outputs
R
S
D
C
Q
1
X
X

0
0
1
X

1
0
0
1

1
0
0
0

0