FDSE

D Flip-Flop with Clock Enable and Synchronous Set

FDSE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Q output High during the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low and CE is High during the Low-to-High clock (C) transition.

For Virtex and Spartan2, the flip-flop is asynchronously preset, output High, when power is applied. For all other devices, the flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.

Inputs				Outputs
S	CE	D	C	Q
1	X	X		1
0	0	X	X	No Chg
0	1	1		1
0	1	0		0

Figure 5.28 FDSE Implementation XC3000, XC4000E, XC4000X, XC5200, Spartan, SpartanXL

Figure 5.29 FDSE Implementation XC9000