Libraries GuideChapter 5: Design Elements (F5MAP to FTSRLE)
FJKCP
J-K Flip-Flop with Asynchronous Clear and Preset
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Spartan2
| Virtex
|
|---|
N/A
| N/A
| N/A
| N/A
| Macro
| N/A
| N/A
| N/A
| N/A
|
FJKCP is a single J-K-type flip-flop with J, K, asynchronous clear (CLR), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous clear input (CLR), when High, overrides all other inputs and resets the Q output Low. The asynchronous preset (PRE) input, when High, overrides all other inputs and sets the Q output High. When CLR and PRE are Low, Q responds to the state of the J and K inputs during the Low-to-High clock transition, as shown in the following truth table.
The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs
| Outputs
|
|---|
CLR
| PRE
| J
| K
| C
| Q
|
|---|
1
| 0
| X
| X
| X
| 0
|
0
| 1
| X
| X
| X
| 1
|
0
| 0
| 0
| 0
| X
| No Chg
|
0
| 0
| 0
| 1
| 
| 0
|
0
| 0
| 1
| 0
|
| 1
|
0
| 0
| 1
| 1
|
| Toggle
|
Figure 5.38 FJKCP Implementation XC9000