Libraries GuideChapter 5: Design Elements (F5MAP to FTSRLE)
FD_1
D Flip-Flop with Negative-Edge Clock
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Spartan2
| Virtex
|
|---|
Macro
| Macro
| Macro
| Macro
| N/A
| Macro
| Macro
| Primitive
| Primitive
|
FD_1 is a single D-type flip-flop with data input (D) and data output (Q). The data on the D input is loaded into the flip-flop during the High-to-Low clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.
Inputs
| Outputs
|
|---|
D
| C
| Q
|
|---|
0
| 
| 0
|
1
|
| 1
|
Figure 5.6 FD_1 Implementation XC3000, XC4000E, XC4000X, XC5200, Spartan, SpartanXL