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| XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Spartan2 | Virtex |
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| N/A | Macro | Macro | N/A | N/A | Macro | Macro | Macro | Macro |
The IFDI_1 D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data input for the flip-flop, which synchronizes data entering the chip. The data on input D is loaded into the flip-flop during the High-to-Low clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or through another external pin.
The flip-flop is asynchronously preset, output High, when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.
For information on legal IFDI, IFDI_1, ILDI, and ILDI_1 combinations, refer to the “ILDI” section.
| Inputs | Outputs | |
|---|---|---|
| D | C | Q |
| 0 |  | 0 |
| 1 | | 1 |
Figure 6.12 IFDI_1 Implementation XC4000E, XC4000X, Spartan, SpartanXLFigure 6.13 IFDI_1 Implementation Spartan2, Virtex