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| XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Spartan2 | Virtex |
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| N/A | N/A | Primitive | N/A | N/A | N/A | Primitive | Primitive | Primitive |
LDPE_1 is a transparent data latch with asynchronous preset, gate enable, and inverted gated. When the asynchronous preset (PRE) is High, it overrides the other input and presets the data (Q) output High. Q reflects the data (D) input while the gate (G) input is Low and gate enable (GE) is High.
If GE is low, data on D cannot be latched. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains High or GE remains Low.
The latch is asynchronously preset, output High, when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.
| Inputs | Outputs | |||
|---|---|---|---|---|
| PRE | GE | G | D | Q |
| 1 | X | X | X | 1 |
| 0 | 0 | X | X | No Chg |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | X | No Chg |
| 0 | 1 |  | D | d |
| d = state of input one setup time prior to Low-to-High gate transition | ||||