OFDEXI

D Flip-Flop with Active-High Enable Output Buffer and Clock Enable (Asynchronous Preset)

OFDEXI is a D flip-flop whose output is enabled by a tristate buffer. The data output (Q) of the flip-flop is connected to the input of an output buffer or OBUFE. The output of the OBUFE (O) is connected to an OPAD or an IOPAD. These flip-flops and buffers are contained in input/output blocks (IOB). The data on the data input (D) is loaded into the flip-flop during the Low-to-High clock (C) transition. When the active-High enable input (E) is High, the data on the flip-flop output (Q) appears on the O output. When E is Low, the output is high impedance (Z state or Off). When CE is Low and E is High, the output does not change.

The flip-flop is asynchronously preset, output High, when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP symbol.

Inputs				Outputs
CE	E	D	C	O
X	0	X	X	Z
1	1	1		1
1	1	0		0
0	1	X	X	No Chg

Figure 8.23 OFDEXI Implementation XC4000E, XC4000X, Spartan, SpartanXL