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Libraries Guide
Chapter 8: Design Elements (OAND2 to OXOR2)

OFDI_1

Output D Flip-Flop with Inverted Clock (Asynchronous Preset)

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Spartan2
Virtex
N/A
Macro
Macro
N/A
N/A
Macro
Macro
Macro
Macro

OFDI_1 exists in an input/output block (IOB). The D flip-flop output (Q) is connected to an OPAD or an IOPAD. The data on the D input is loaded into the flip-flop during the High-to-Low clock (C) transition and appears on the Q output.

The flip-flop is asynchronously preset, output High, when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.

Inputs
Outputs
D
C
Q
D

d
d = state of referenced input one setup time prior to the active clock transition

Figure 8.27 OFDI_1 Implementation XC4000E, XC4000X, Spartan, SpartanXL

Figure 8.28 OFDI_1 Implementation Spartan2, Virtex