OFDTI

D Flip-Flop with Active-Low 3-State Output Buffer (Asynchronous Preset)

OFDTI and its output buffer are contained in an input/output block (IOB). The data output of the flip-flop (Q) is connected to the input of an output buffer (OBUFT). The output of the OBUFT is connected to an OPAD or an IOPAD. The data on the data input (D) is loaded into the flip-flop on the Low-to-High clock (C) transition. When the active-Low enable input (T) is Low, the data on the flip-flop output (Q) appears on the output (O). When T is High, the output is high impedance (off).

The flip-flop is asynchronously preset, output High, when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP symbol.

Inputs			Outputs
T	D	C	O
1	X	X	Z
0	1		1
0	0		0

Figure 8.35 OFDTI Implementation XC4000E, XC4000X, Spartan, SpartanXL