Libraries GuideChapter 8: Design Elements (OAND2 to OXOR2)
OFDXI_1
Output D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Spartan2
| Virtex
|
|---|
N/A
| Macro
| Macro
| N/A
| N/A
| Macro
| Macro
| Macro
| Macro
|
OFDXI_1 is located in an input/output block (IOB). The D flip-flop output (Q) is connected to an OPAD or an IOPAD. The data on the D input is loaded into the flip-flop during the High-to-Low clock (C) transition and appears on the Q output. When CE is Low, the output (Q) does not change.
The flip-flop is asynchronously preset with High output when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.
Inputs
| Outputs
|
|---|
CE
| D
| C
| Q
|
|---|
1
| D
| 
| d
|
0
| X
| X
| No Chg
|
d = state of referenced input one setup time prior to active clock transition
|
Figure 8.45 OFDXI_1 Implementation XC4000E, XC4000X, Spartan, SpartanXL