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| Element | XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Spartan2 | Virtex |
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| OR2, OR2B1, OR2B2, OR3, OR3B1, OR3B2, OR3B3, OR4, OR4B1, OR4B2, OR4B3, OR4B4 | Primitive | Primitive | Primitive | Primitive | Primitive | Primitive | Primitive | Primitive | Primitive |
| OR5, OR5B1, OR5B2, OR5B3, OR5B4, OR5B5 | Primitive | Primitive | Primitive | Macro | Primitive | Primitive | Primitive | Primitive | Primitive |
| OR6, OR7, OR8, OR9 | Macro | Macro | Macro | Macro | Primitive | Macro | Macro | Macro | Macro |
Figure 8.48 OR Gate RepresentationsThe OR function is performed in the Configurable Logic Block (CLB) function generators for FPGAs. OR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. OR functions of six to nine inputs are available with only non-inverting inputs. To invert some or all inputs, use external inverters. Since each input uses a CLB resource, replace functions with unused inputs with functions having the necessary number of inputs.
Refer to the “OR12, 16” section for information on additional OR functions for the XC5200, Spartan2, and Virtex.
Figure 8.49 OR5 Implementation XC5200Figure 8.50 OR8 Implementation XC3000Figure 8.51 OR8 Implementation XC4000E, XC4000X, XC5200, Spartan, SpartanXLFigure 8.52 OR8 Implementation Spartan2, Virtex